Rui Chen

US Patent:

20210369776, Dec 2, 2021

Filed:

Dec 5, 2019

Appl. No.:

17/311114

Inventors:

- Guangzhou, Guangdong, CN
- Chapel Hill NC, US
Paul Bryson - Culver City CA, US
Peter Alexander - Durham NC, US
Rui Chen - Durham NC, US

International Classification:

A61K 35/17
C07K 14/725
C07K 16/30
A61K 45/06

Abstract:

The present disclosure is directed towards genetically engineered TCR-T cells to recognize tumor antigens and simultaneously secrete a binding protein that blocks an immune checkpoint molecule and TGF-beta. These engineered T cells demonstrate stronger antitumor response and reduced T cell exhaustion. The present disclosure provides immunotherapy against HPV- or EBV-positive cancers, among others.

US Patent:

20180006650, Jan 4, 2018

Filed:

Dec 2, 2016

Appl. No.:

15/367706

Inventors:

- San Diego CA, US
Rakesh Vattikonda - San Diego CA, US
De Lu - San Diego CA, US
Samrat Sinharoy - San Diego CA, US
Rui Chen - San Diego CA, US

International Classification:

H03K 19/0185
H03K 19/00
H03K 3/356

Abstract:

In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

US Patent:

20180006651, Jan 4, 2018

Filed:

Dec 2, 2016

Appl. No.:

15/367751

Inventors:

- San Diego CA, US
Rakesh Vattikonda - San Diego CA, US
De Lu - San Diego CA, US
Samrat Sinharoy - San Diego CA, US
Rui Chen - San Diego CA, US

International Classification:

H03K 19/0185
H03K 19/00

Abstract:

In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.