Changyuan Chen

US Patent:

7247907, Jul 24, 2007

Filed:

May 20, 2005

Appl. No.:

11/134557

Inventors:

Feng Gao - Sunnyvale CA, US
Ya-Fen Lin - Santa Clara CA, US
John W. Cooksey - Brentwood CA, US
Changyuan Chen - Sunnyvale CA, US
Yuniarto Widjaja - San Jose CA, US
Dana Lee - Santa Clara CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29/788

US Classification:

257315, 257316, 257321, 257324, 257326, 438201, 438257, 438258

Abstract:

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

US Patent:

7358559, Apr 15, 2008

Filed:

Sep 29, 2005

Appl. No.:

11/239791

Inventors:

Felix (Ying-Kit) Tsui - Cupertino CA, US
Jeng-Wei Yang - Jhubei, TW
Bomy Chen - Cupertino CA, US
Chun-Ming Chen - Banciao, TW
Dana Lee - Santa Clara CA, US
Changyuan Chen - Sunnyvale CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29/788

US Classification:

257315, 257314, 257316, 257324, 438259, 438261, 438266

Abstract:

A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material.

US Patent:

7544569, Jun 9, 2009

Filed:

Sep 5, 2006

Appl. No.:

11/516431

Inventors:

Feng Gao - Sunnyvale CA, US
Ya-Fen Lin - Santa Clara CA, US
John W. Cooksey - Brentwood CA, US
Changyuan Chen - Sunnyvale CA, US
Yuniarto Widjaja - San Jose CA, US
Dana Lee - Santa Clara CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 21/336

US Classification:

438266, 438257, 438258, 438261, 438262, 438264, 438287, 438288, 438622, 438672, 257E21679, 257E21681

Abstract:

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

US Patent:

7723774, May 25, 2010

Filed:

Jul 10, 2007

Appl. No.:

11/775851

Inventors:

Changyuan Chen - Sunnyvale CA, US
Ya-Fen Lin - Saratoga CA, US
Dana Lee - Saratoga CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29/788

US Classification:

257315, 257316, 257319, 257E2168

Abstract:

Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

US Patent:

7808839, Oct 5, 2010

Filed:

Jun 6, 2007

Appl. No.:

11/810714

Inventors:

Yuniarto Widjaja - San Jose CA, US
John W. Cooksey - Brentwood CA, US
Changyuan Chen - Sunnyvale CA, US
Feng Gao - Sunnyvale CA, US
Ya-Fen Lin - Santa Clara CA, US
Dana Lee - Santa Clara CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C 16/04

US Classification:

36518529, 36518518, 36518505

Abstract:

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

US Patent:

8164135, Apr 24, 2012

Filed:

May 4, 2010

Appl. No.:

12/773811

Inventors:

Changyuan Chen - Sunnyvale CA, US
Ya-Fen Lin - Saratoga CA, US
Dana Lee - Saratoga CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29/788

US Classification:

257316, 257315, 257319, 257E2168

Abstract:

Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

US Patent:

8174895, May 8, 2012

Filed:

Dec 15, 2009

Appl. No.:

12/638853

Inventors:

Changyuan Chen - Sunnyvale CA, US
Jeffrey Lutze - San Jose CA, US
Yingda Dong - San Jose CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 16/04

US Classification:

36518519, 36518518, 36518522, 36518524, 36518503, 36518517

Abstract:

A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

US Patent:

8456915, Jun 4, 2013

Filed:

Mar 30, 2012

Appl. No.:

13/436805

Inventors:

Changyuan Chen - Sunnyvale CA, US
Jeffrey Lutze - San Jose CA, US
Yingda Dong - San Jose CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 11/34

US Classification:

36518518, 36518519, 3651852, 36518522, 36518524, 36518503

Abstract:

A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.