Zuxu L Qin

US Patent:

8243866, Aug 14, 2012

Filed:

May 7, 2008

Appl. No.:

12/116329

Inventors:

Dawei Huang - San Diego CA, US
Zuxu Qin - Sunnyvale CA, US
Drew G. Doblar - San Jose CA, US
Waseem Ahmad - Union City CA, US
Dong Joon Yoon - San Jose CA, US
Osman Javed - Santa Clara CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

H04L 7/00
H04L 27/06

US Classification:

375355, 375340

Abstract:

An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

US Patent:

8452829, May 28, 2013

Filed:

Jun 23, 2008

Appl. No.:

12/144610

Inventors:

Dawei Huang - San Diego CA, US
Dong J. Yoon - Santa Clara CA, US
Osman Javed - Pleasanton CA, US
Zuxu Qin - Sunnyvale CA, US
Deqiang Song - San Diego CA, US
Daniel J. Beckman - Chula Vista CA, US
Drew G. Doblar - San Jose CA, US
Waseem Ahmad - Union City CA, US
Andrew Keith Joy - Great Houghton, GB
Simon Dennis Forey - Earls Barton, GB
William Franklin Leven - Dallas TX, US
Nirmal C. Warke - Irving TX, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 17/10

US Classification:

708322, 375232

Abstract:

A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.

US Patent:

8634500, Jan 21, 2014

Filed:

Mar 27, 2012

Appl. No.:

13/431009

Inventors:

Zuxu Qin - Palo Alto CA, US
Rajesh Kumar - Campbell CA, US
Dawei Huang - San Diego CA, US
Jing Shi - Carlsbad CA, US
Deqiang Song - San Diego CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

H03K 9/00

US Classification:

375316, 341143, 375317, 375318

Abstract:

A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.

US Patent:

20040098690, May 20, 2004

Filed:

Nov 20, 2002

Appl. No.:

10/301365

Inventors:

Mathew Joseph - Milpitas CA, US
Zuxu Qin - Stanford CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F017/50

US Classification:

716/012000

Abstract:

A method and apparatus is provided by which a die designer can efficiently evaluate package routings associated with a die connection bump layout of a die. The die designer is equipped to determine appropriate placement of die connection bumps around a periphery of the die, designate signal and power assignments for die connection bumps, and check routings between die connection bumps and associated package pins. The die designer can efficiently iterate, without recourse to a package designer, through numerous die connection bump placement and assignment configurations to develop a die connection bump layout that is routable within a package. Thus, time required for iteration between the die designer and the package designer to establish a proper placement and assignment of die connection bumps is substantially reduced. Also, as design variables and constraints change during a die design process, the die designer can efficiently re-evaluate a die-to-package interface without recourse to the package designer.

US Patent:

20100283535, Nov 11, 2010

Filed:

Apr 30, 2010

Appl. No.:

12/771944

Inventors:

Minsheng Li - Santa Clara CA, US
Gong Tom Lei - Austin TX, US
Song Liu - Cupertino CA, US
Jun Xiong - Santa Clara CA, US
Yincai Liu - Santa Clara CA, US
Feiqin Yang - Fremont CA, US
ZuXu Qin - Sunnyvale CA, US

Assignee:

FutureWei Technologies, Inc. - Plano TX

International Classification:

G05F 1/10

US Classification:

327537, 327535

Abstract:

In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node.

US Patent:

20190056760, Feb 21, 2019

Filed:

Aug 16, 2017

Appl. No.:

15/678811

Inventors:

- Redwood City CA, US
Philip P. Kwan - San Francisco CA, US
Zuxu Qin - Palo Alto CA, US

International Classification:

G06F 1/10
H03L 7/18
H03K 19/0185

Abstract:

A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.

US Patent:

20170222796, Aug 3, 2017

Filed:

Feb 1, 2016

Appl. No.:

15/012518

Inventors:

- Redwood City CA, US
Zuxu Qin - Stanford CA, US
Nima Edelkhani - San Jose CA, US

International Classification:

H04L 7/033

Abstract:

Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.