Yongtao You

US Patent:

56548982, Aug 5, 1997

Filed:

Jul 11, 1995

Appl. No.:

8/500579

Inventors:

Bradley R. Roetcisoender - Kirkland WA
Yongtao You - Bellevue WA
Richard K. McGehee - Bellevue WA

Assignee:

Cascade Design Automation Corporation - Bellevue WA

International Classification:

G06F 1750

US Classification:

364490

Abstract:

A method and apparatus for determining the layout of an integrated circuit, in accordance with timing constraints, by means of sizing the buffers in the layout. A nominal netlist for the layout of the integrated circuit is used to determine critical paths through the circuit. The time-critical paths are determined and the instances of the buffers along the path are resized so that the time delays in the time-critical paths are either brought within the predetermined timing criteria, or no further improvement in any time-critical path is possible.

Address:

15016 SE 63 St, Bellevue, WA 98006

VIN:

JM1BK344491211744

Make:

MAZDA

Model:

MAZDA3

Year:

2009