Yi Feng Ma

US Patent:

7998846, Aug 16, 2011

Filed:

Sep 12, 2008

Appl. No.:

12/209478

Inventors:

Eunha Kim - Menlo Park CA, US
Jeremy Wahl - Sunnyvale CA, US
Shenqing Fang - Fremont CA, US
YouSeok Suh - Cupertino CA, US
Kuo-Tung Chang - Saratoga CA, US
Yi Ma - Santa Clara CA, US
Rinji Sugino - San Jose CA, US
Jean Yang - Glendale CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/263

US Classification:

438487, 438486, 438489, 438799, 438478, 257E21028, 257E21134, 257E21347

Abstract:

A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i. e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

US Patent:

20090065816, Mar 12, 2009

Filed:

Sep 8, 2008

Appl. No.:

12/206390

Inventors:

KEVIN L. CUNNINGHAM - Palo Alto CA, US
Yi Ma - Santa Clara CA, US
Majeed A. Foad - Sunnyvale CA, US

International Classification:

H01L 21/20
H01L 29/04
H01L 29/78

US Classification:

257255, 438482, 257627, 257E2109, 257E29004, 257E29255

Abstract:

In certain embodiments a method of forming a multi-layer silicon film is provided. A substrate is placed in a process chamber. An amorphous silicon film is formed on the substrate by flowing into the process chamber a first process gas comprising a silicon source gas. A polysilicon film is formed on the amorphous silicon film by flowing into the deposition chamber a first process gas mix comprising a silicon source gas and a first dilution gas mix comprising Hand an inert gas at a first temperature. In certain embodiments, the polysilicon film has a crystal orientation which is dominated by the direction. In certain embodiments, the polysilicon film has a crystal orientation dominated by the orientation. Structures comprising a lower amorphous silicon film and an upper polysilicon film having a random grain structure or a columnar grain structure are provided as well.

US Patent:

20110272775, Nov 10, 2011

Filed:

Jul 14, 2011

Appl. No.:

13/183373

Inventors:

Eunha KIM - Menlo Park CA, US
Jeremy WAHL - Sunnyvale CA, US
Shenqing FANG - Fremont CA, US
YouSeok SUH - Cupertino CA, US
Kuo-Tung CHANG - Saratoga CA, US
Yi MA - Santa Clara CA, US
Rinji SUGINO - San Jose CA, US
Jean YANG - Glendale CA, US

International Classification:

H01L 29/02

US Classification:

257499, 257622, 257E29002

Abstract:

A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

US Patent:

20160118585, Apr 28, 2016

Filed:

Jan 7, 2016

Appl. No.:

14/990550

Inventors:

- Sunnyvale CA, US
John E. Sanchez - Palo Alto CA, US
Wei Ti Lee - San Jose CA, US
Yi Ma - Santa Clara CA, US
Venkatesh P. Gopinath - Fremont CA, US
Foroozan Sarah Koushan - San Jose CA, US

International Classification:

H01L 45/00

Abstract:

In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

US Patent:

20140246641, Sep 4, 2014

Filed:

Mar 14, 2013

Appl. No.:

13/829941

Inventors:

ADESTO TECHNOLOGIES CORPORATION - , US
John E. Sanchez - Palo Alto CA, US
Wei Ti Lee - San Jose CA, US
Yi Ma - Santa Clara CA, US
Venkatesh P. Gopinath - Fremont CA, US
Foroozan Sarah Koushan - San Jose CA, US

Assignee:

ADESTO TECHNOLOGIES CORPORATION - Sunnyvale CA

International Classification:

H01L 45/00

US Classification:

257 4, 438382

Abstract:

In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

Author:

Yi Ma

ISBN #:

0387008934

Author:

Yi Ma

ISBN #:

3540709312