Sang-Joon John Lee - Stanford CA, US Jun Sasahara - Saitama, JP Nariaki Kuriyama - Saitama, JP Tadahiro Kubota - Saitama, JP Toshifumi Suzuki - Tokyo, JP Friedrich B. Prinz - Stanford CA, US Suk Won Cha - Stanford CA, US Amy Chang-Chien - Stanford CA, US Yaocheng Liu - Stanford CA, US Ryan O'Hayre - Stanford CA, US
Assignee:
Honda Giken Kogyo Kabushiki Kaisha - Tokyo The Board of Trustees of the Lealand Stanford Junior University - Palo Alto CA
International Classification:
H01M 2/14 H01M 2/08 H01M 2/00 H01M 8/10
US Classification:
429 38, 429 35, 429 34, 429 32
Abstract:
In a fuel cell assembly comprising a plurality of cell each including an electrolyte layer (), a pair of diffusion electrode layers () interposing the electrolyte layer between them, and a pair of flow distribution plates () for defining passages () for fuel and oxidant fluids that contact the diffusion electrode layers, the fuel cells are arranged on a common plane. Therefore, the vertical dimension of the fuel cell assembly can be minimized, and a fuel cell assembly of favorable electric properties can be achieved. Each flow distribution plate is typically formed with communication passages for communicating fluid passages defined on each side of the electrolyte layer at a prescribed pattern. The communication passages and through holes communicate the fluid passages in such a manner that adjacent fuels cells have opposite polarities.
Yuji Saito - Wako, JP Jun Sasahara - Wako, JP Nariaki Kuriyama - Wako, JP Tadahiro Kubota - Wako, JP Toshifumi Suzuki - Wako, JP Yuji Isogai - Wako, JP Friedrich B. Prinz - Stanford CA, US Sang-Joon John Lee - Stanford CA, US Suk Won Cha - Stanford CA, US Yaocheng Liu - Stanford CA, US Ryan O'Hayre - Stanford CA, US
Assignee:
Honda Giken Kogyo Kabushiki Kaisha - Tokyo Stanford University - Palo Alto CA
International Classification:
H01M 8/10 H01M 4/88
US Classification:
429 31, 429 34, 429 40, 502101
Abstract:
In a fuel cell comprising a tubular casing, an electrolyte layer received in the tubular casing, and a pair of gas diffusion electrodes interposing the electrolyte layer and defining a fuel gas passage and an oxidizing gas passage, respectively, each gas diffusion electrode is formed by stacking a plurality of layers of material therefor, for instance in the axial direction of the casing. Because the gas diffusion layers are formed layer by layer, components can be formed in highly fine patterns so that a highly compact tubular fuel cell can be achieved. Similarly, the dimensions of the various elements of the fuel cell can be controlled in a highly accurate manner. Also, the geometric arrangement can be changed at will in intermediate parts of each gas passage.
Yuji Saito - Wako, JP Jun Sasahara - Wako, JP Nariaki Kuriyama - Wako, JP Tadahiro Kubota - Wako, JP Toshifumi Suzuki - Wako, JP Yuji Isogai - Wako, JP Friedrich B. Prinz - Stanford CA, US Sang-Joon John Lee - Stanford CA, US Suk Won Cha - Stanford CA, US Yaocheng Liu - Stanford CA, US Ryan O'Hayre - Stanford CA, US
Assignee:
Honda Giken Kogyo Kabushiki Kaisha - Tokyo Stanford University - Palo Alto CA
International Classification:
H01M 8/10 H01M 8/22
US Classification:
429 31, 429 32, 429 40
Abstract:
In a fuel cell comprising a tubular casing, an electrolyte layer received in the tubular casing, and a pair of gas diffusion electrodes interposing the electrolyte layer and defining a fuel gas passage and an oxidizing gas passage, respectively, each gas diffusion electrode is formed by stacking a plurality of layers of material therefor, for instance in the axial direction of the casing. Because the gas diffusion layers are formed layer by layer, components can be formed in highly fine patterns so that a highly compact tubular fuel cell can be achieved. Similarly, the dimensions of the various elements of the fuel cell can be controlled in a highly accurate manner. Also, the geometric arrangement can be changed at will in intermediate parts of each gas passage.
N-Channel Mosfets Comprising Dual Stressors, And Methods For Forming The Same
Jinghong H. Li - Poughquag NY, US Yaocheng Liu - Elmsford NY, US Zhijiong Luo - Carmel NY, US Anita Madan - Danbury CT, US Nivo Rovedo - Lagrangeville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
Raised Sti Structure And Superdamascene Technique For Nmosfet Performance Enhancement With Embedded Silicon Carbon
Ashima B. Chakravarti - Hopewell Junction NY, US Dureseti Chidambarrao - Weston CT, US Judson R. Holt - Wappingers Falls NY, US Yaocheng Liu - Elmsford NY, US Kern Rim - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/8238
US Classification:
438199, 257E2913
Abstract:
An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
N-Channel Mosfets Comprising Dual Stressors, And Methods For Forming The Same
Jinghong H. Li - Poughquag NY, US Yaocheng Liu - Elmsford NY, US Zhijiong Luo - Carmel NY, US Anita Madan - Danbury CT, US Nivo Rovedo - LaGrangeville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/22
US Classification:
438303, 438305, 438549
Abstract:
The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
Control Of Poly-Si Depletion In Cmos Via Gas Phase Doping
Yaocheng Liu - Elmsford NY, US Alexander Reznicek - Mount Kisco NY, US Devendra K. Sadana - Pleasantville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/3205 H01L 21/4763
US Classification:
438592, 438585, 438593, 257412, 257413
Abstract:
A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
After Gate Fabrication Of Field Effect Transistor Having Tensile And Compressive Regions
Dureseti Chidambarrao - Weston CT, US William K. Henson - Beacon NY, US Yaocheng Liu - Elmsford NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/8238
US Classification:
438197, 438154, 257E21632
Abstract:
A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overlies the gate and the active semiconductor region. Then, the SOI substrate is heated to cause a flowable dielectric material in a buried dielectric layer of the SOI substrate to soften and reflow. As a result of the reflowing, the sacrificial stressed layer induces stress in a channel region of the active semiconductor region underlying the gate. A source region and a drain region are formed in the active semiconductor region, desirably after removing the sacrificial stressed layer.