Chunbo B Liu

US Patent:

7471118, Dec 30, 2008

Filed:

May 11, 2007

Appl. No.:

11/747246

Inventors:

Chunbo Liu - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G01R 19/00
H03K 5/153

US Classification:

327 58, 327 77, 327 81, 327 89

Abstract:

An apparatus comprising a first comparator circuit, a second comparator circuit, a third comparator circuit, and a difference circuit. The first comparator circuit may be configured to generate a first intermediate current in response to a first input voltage and a second input voltage. The second comparator circuit may be configured to generate a second intermediate current in response to the first input voltage and the second input voltage. The third comparator circuit may be configured to generate an intermediate reference current in response to a first reference voltage and a second reference voltage. The difference circuit may be configured to generate a first compare voltage and a second compare voltage in response to the first intermediate current, the second intermediate current, and the intermediate reference current. The apparatus may indicate a squelch condition when the first compare voltage is greater than the second compare voltage.

US Patent:

7472322, Dec 30, 2008

Filed:

May 31, 2005

Appl. No.:

11/141223

Inventors:

Zhijian Ma - Cupertino CA, US
Chunbo Liu - San Jose CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

G01R 31/317
G01R 31/40

US Classification:

714724, 714735, 438234

Abstract:

A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can test a single transistor or can test multiple transistors. A testing method is disclosed in which a supply voltage is applied to the waveform generator to produce pulses that are applied to the gate of a transistor to be tested. A bias voltage is applied to the source and drain of the transistor to be tested, and the charge pumping current that is generated at the substrate is then measured. The process can be repeated at different bias voltage levels to obtain additional current measurements, indicating the maximum charge pumping current for the transistor that is being tested. The determined maximum charge pumping current can then be used for determining whether there is excessive 1/f noise in the device under test.

US Patent:

7589594, Sep 15, 2009

Filed:

Oct 27, 2005

Appl. No.:

11/260442

Inventors:

Chunbo Liu - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03L 7/00

US Classification:

331 16, 331 1 A, 331 34, 331179, 327156

Abstract:

An apparatus comprising a voltage controlled oscillator, a first charge pump, a second charge pump, a switch circuit and a comparator circuit. The voltage controlled oscillator may be configured to generate an output signal oscillating at a first frequency in response to a control signal. The charge pump circuit may be configured to generate a first component of the control signal in response to a first adjustment signal and a second adjustment signal. The second charge pump may be configured to generate a second component of the control signal in response to a first intermediate signal and a second intermediate signal. The switch circuit may be configured to generate the first intermediate signal and the second intermediate signal in response to the first adjustment signal and the second adjustment signal. The comparator circuit may be configured to generate the first and second adjustment signals in response to a comparison between (i) an input signal having a second frequency and (ii) the output signal.

US Patent:

8120431, Feb 21, 2012

Filed:

Jun 19, 2009

Appl. No.:

12/487873

Inventors:

Chunbo Liu - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03L 7/00

US Classification:

331 16, 331 11, 331 17, 331 34

Abstract:

An apparatus comprising a voltage controlled oscillator, a first charge pump, a second charge pump, a switch circuit and a comparator circuit. The voltage controlled oscillator may be configured to generate an output signal oscillating at a first frequency in response to a control signal. The charge pump circuit may be configured to generate a first component of the control signal in response to a first adjustment signal and a second adjustment signal. The second charge pump may be configured to generate a second component of the control signal in response to a first intermediate signal and a second intermediate signal. The switch circuit may be configured to generate the first intermediate signal and the second intermediate signal in response to the first adjustment signal and the second adjustment signal. The comparator circuit may be configured to generate the first and second adjustment signals in response to a comparison between (i) an input signal having a second frequency and (ii) the output signal.

US Patent:

20140049232, Feb 20, 2014

Filed:

Jul 9, 2013

Appl. No.:

13/937943

Inventors:

Gang Chen - Taipo, HK
Chunbo Liu - San Jose CA, US
Gabor Reizik - Dublin CA, US

Assignee:

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - PHOENIX AZ

International Classification:

G05F 1/10

US Classification:

323234

Abstract:

In one embodiment, a method of forming a ripple suppressor circuit includes a configuring the ripple suppressor circuit to receive a first signal that is representative of a requested voltage and a second signal that is a filtered value of the first signal. The method also includes configuring the ripple suppressor circuit to determine a peak value of the second signal responsively to the first signal and to determine a minimum value of the second signal responsively to the first signal. The method may also include configuring the ripple suppressor circuit to form an average value of the peak value and the minimum value.

US Patent:

6898561, May 24, 2005

Filed:

Dec 21, 1999

Appl. No.:

09/465433

Inventors:

Chunbo Liu - San Jose CA, US
Zhijian Ma - San Jose CA, US
Jeong Yeol Choi - Palo Alto CA, US

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G06F017/50

US Classification:

703 14

Abstract:

Methods, apparatus and computer program products for modeling integrated circuits having dense devices therein that experience linewidth (e. g. , gate electrodes) reductions during fabrication are provided. For dense devices having electrical paths therein and first and second gate electrodes that overlie the electrical path, operations include determining an electrical gate length of the first gate electrode by evaluating a change in current through the electrical path relative to a change in gate length of the second gate electrode. The operation to determine the electrical gate length of the first gate electrode includes evaluating a change in simulated drain-to-source current through the electrical path relative to a change in the electrical gate length of the second gate electrode.

US Patent:

20210357047, Nov 18, 2021

Filed:

Jul 27, 2021

Appl. No.:

17/386259

Inventors:

- San Jose CA, US
Chunbo Liu - San Jose CA, US

Assignee:

Synaptics Incorporated - San Jose CA

International Classification:

G06F 3/044

Abstract:

A processing system is disclosed. The processing system includes an amplifier configured to generate a feedback signal including a spatial common mode estimate from spatial-common-mode-processed signals. The processing system further includes charge integrators configured to obtain resulting signals from capacitive sensor electrodes, the resulting signals including a spatial common mode, and generate the spatial-common-mode-processed signals by mitigating the spatial common mode in the resulting signals using the feedback signal. The processing system also includes a controller including a programmable gain amplifier capturing the spatial common mode estimate over a summing resistor of the amplifier and a demodulator configured to remove a modulation voltage from the spatial common mode estimate.

US Patent:

20210294454, Sep 23, 2021

Filed:

Jun 7, 2021

Appl. No.:

17/341124

Inventors:

- San Jose CA, US
Chunbo Liu - San Jose CA, US

Assignee:

Synaptics Incorporated - San Jose CA

International Classification:

G06F 3/041
G06F 3/044

Abstract:

A processing system is disclosed. The processing system includes an amplifier including a multitude of input resistors receiving a multitude of reduced noise signals from a multitude of charge integrators and a summing resistor at an output of the amplifier. The amplifier is configured to generate a feedback signal at the output of the amplifier by amplifying each of a multitude of reduced noise signals using a gain value and a cardinality of the multitude of reduced noise signals. The multitude of charge integrators is configured to obtain a multitude of resulting signals from a multitude of capacitive sensor electrodes coupled to a noise source and generate the multitude of reduced noise signals by mitigating noise in the multitude of the resulting signals, at the multitude of charge integrators, using the feedback signal. Resistances of the multitude of input resistors, a resistance of the summing resistor, and the gain values are selected to mitigate the noise.