Wing Y Cheung

US Patent:

7688815, Mar 30, 2010

Filed:

Aug 17, 2004

Appl. No.:

10/920789

Inventors:

Jan Bialkowski - San Jose CA, US
Wing Cheung - Fremont CA, US

Assignee:

BarracudaNetworks Inc - Campbell CA

International Classification:

H04L 12/50

US Classification:

370388, 370412

Abstract:

An interconnect switch stores data messages received from one or more source devices and prioritizes the data messages received from each source device based on the order that the data messages were received from the source device. For each available destination device associated with the interconnect switch, the interconnect switch identifies the data messages with the highest priority that are to be routed to the available destination device and selects one of the identified data messages for the available destination device. The interconnect switch then routes the selected data messages to the available destination devices.

US Patent:

8446914, May 21, 2013

Filed:

Apr 22, 2011

Appl. No.:

13/092864

Inventors:

Joseph Juh-En Cheng - Palo Alto CA, US
Wing Cheung - Fremont CA, US
John Michael Terry - San Jose CA, US
Suresh Vobbilisetty - San Jose CA, US
Surya P. Varanasi - Dublin CA, US
Parviz Ghalambor - Los Altos CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

H04L 12/56

US Classification:

370401, 370217, 370244, 370392

Abstract:

One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.

US Patent:

20050044321, Feb 24, 2005

Filed:

Aug 17, 2004

Appl. No.:

10/921002

Inventors:

Jan Bialkowski - San Jose CA, US
Wing Cheung - Fremont CA, US

International Classification:

G06F012/00

US Classification:

711118000, 711167000

Abstract:

A cache management system in a multiprocessing computing system avoids blocking subsequent memory requests to access data in the cache after a previous memory request to access the data in the cache generates a cache miss and while the cache is being updated with the data. The previous memory request and subsequent memory requests are stored in a piggyback FIFO while the data is retrieved from a memory device. The cache is then updated with the data and the previous memory request and subsequent memory requests are processed on the cache.

US Patent:

20110299414, Dec 8, 2011

Filed:

Mar 15, 2011

Appl. No.:

13/048817

Inventors:

Shunjia Yu - San Jose CA, US
Anoop Ghanwani - Rocklin CA, US
Phanidhar Koganti - Sunnyvale CA, US
John Michael Terry - San Jose CA, US
Wing Cheung - Fremont CA, US
Joseph Juh-En Cheng - Palo Alto CA, US
Surya P. Varanasi - Dublin CA, US

Assignee:

BROCADE COMMUNICATIONS SYSTEMS, INC. - San Jose CA

International Classification:

H04L 12/26

US Classification:

370252

Abstract:

Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.

US Patent:

20110299533, Dec 8, 2011

Filed:

Mar 17, 2011

Appl. No.:

13/050102

Inventors:

Shunjia Yu - San Jose CA, US
Anoop Ghanwani - Rocklin CA, US
Phanidhar Koganti - Sunnyvale CA, US
Mythilikanth Raman - San Jose CA, US
Rajiv Krishnamurthy - San Jose CA, US
John Michael Terry - San Jose CA, US
Wing Cheung - Fremont CA, US
Joseph Juh-En Cheng - Palo Alto CA, US
Surya P. Varanasi - Dublin CA, US

Assignee:

BROCADE COMMUNICATIONS SYSTEMS, INC. - San Jose CA

International Classification:

H04L 12/56

US Classification:

370392

Abstract:

Systems and techniques for processing and forwarding packets are described. Some embodiments provide a system (e.g., a switch) which determines an internal virtual network identifier and/or an internal policy identifier for a packet based on a port on which the packet was received and/or one or more fields in the packet. The system can then process and forward the packet based on the internal virtual network identifier and/or internal policy identifier. In some embodiments, the system encapsulates the packet in a TRILL (Transparent Interconnection of Lots of Links) packet by adding a TRILL header to the packet. In some embodiments, the scope of an internal virtual network identifier and/or an internal policy identifier may not extend beyond a switch or a module within a switch.

US Patent:

20120106365, May 3, 2012

Filed:

Oct 29, 2010

Appl. No.:

12/916060

Inventors:

John Michael Terry - San Jose CA, US
Wing Cheung - Fremont CA, US
Surya Prakash Varanasi - Dublin CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

H04L 12/26

US Classification:

370252

Abstract:

A solution for network packet latency measurement includes, at a network device having a memory, storing a first time value indicating when an ingress port of the network device received a packet. The solution also includes storing a second time value indicating when an egress port of the network device received the packet for transmission towards another network device. The solution also includes storing a difference between the first time value and the second time value.

US Patent:

20120110411, May 3, 2012

Filed:

Oct 29, 2010

Appl. No.:

12/916384

Inventors:

Wing Cheung - Fremont CA, US
Joseph Juh-En Cheng - Palo Alto CA, US
John Michael Terry - San Jose CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

G11C 29/52
H03M 13/29
H03M 13/05
G11C 15/00
G06F 11/10

US Classification:

714758, 365 491, 365 4917, 714763, 714807, 714E11034

Abstract:

A memory system including a content addressable memory (CAM) array and a non-CAM array. The non-CAM array, which may share word lines with the CAM array, stores one or more error detection bits associated with each row of the CAM array. A state machine reads entries of the CAM array and corresponding error detection bits of the non-CAM array during idle cycles of the CAM array. Error detection logic identifies errors in the entries read from CAM array (using the retrieved error detection bits). If these errors are correctable, the error detection logic corrects the entry, and writes the corrected entry back to the CAM array (an updated set of error detection bits are also written to the non-CAM array). If these errors are not correctable, an interrupt is generated, which causes correct data to be retrieved from a shadow copy of the CAM array.

US Patent:

20130031077, Jan 31, 2013

Filed:

Oct 28, 2011

Appl. No.:

13/284829

Inventors:

Jian Liu - Palo Alto CA, US
Philip Lynn Leichty - Rochester MN, US
How Tung Lim - San Jose CA, US
John Michael Terry - San Jose CA, US
Mahesh Srinivasa Maddury - San Jose CA, US
Wing Cheung - Fremont CA, US
Kung Ling Ko - Union City CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

G06F 17/30

US Classification:

707706, 707E17108

Abstract:

A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.