Hung Cheung

US Patent:

20080012605, Jan 17, 2008

Filed:

Jul 12, 2006

Appl. No.:

11/485225

Inventors:

Hung K. Cheung - Fremont CA, US

International Classification:

G06F 1/08

US Classification:

327 99

Abstract:

A glitch-free, clock switching circuit in which an asynchronous, sequential logic circuit has as inputs a clock select signal and a pair of clock signals. A plurality of operating state variable signals are generated in the sequential logic circuit in response to transitions in the input signal. A combinational logic clock output circuit is responsive to the input clock signals and predetermined ones of the operating state variable signals for outputting a newly selected clock signal only when said predetermined operating state variable signals indicate the sensing of a falling edge of the currently outputted clock signal followed by a falling edge of the newly selected clock signal.

US Patent:

7197104, Mar 27, 2007

Filed:

Feb 18, 2004

Appl. No.:

10/781560

Inventors:

Hung K. Cheung - Fremont CA, US
Hee Wong - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 23/00

US Classification:

377118, 377119

Abstract:

An edge counter counting both rising and falling edges of an input signal is implemented with combinational logic, without using flip-flops. The combinational logic is designed using intermediate signals and state transitions producing an output signal having a cycle corresponding to a predetermined odd or even number of input signal edges, with the logic optimized and protected against entry into “stuck” states. A low power, low gate count edge counter is thus implemented with an output signal duty cycle at least as balanced as the input counter duty cycle.