William K Cheung

Author:

William Cheung

ISBN #:

0897501071

Author:

William Cheung

ISBN #:

0897501101

Author:

William Cheung

ISBN #:

0897501187

Author:

William Cheung

ISBN #:

0897501241

Author:

William Cheung

ISBN #:

0897501306

Author:

William Cheung

ISBN #:

2884790039

Author:

William Cheung

ISBN #:

2884790063

Author:

William Cheung

ISBN #:

2884790098

US Patent:

7308610, Dec 11, 2007

Filed:

Dec 10, 2004

Appl. No.:

11/009166

Inventors:

Rajendra Kuramkote - Newcastle WA, US
Suresh Marisetty - San Jose CA, US
Koichi Yamada - Los Gatos CA, US
Scott Brenden - Bothell WA, US
William Cheung - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 38

Abstract:

A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a component of the processing system, and may generate abstracted error data, based at least in part on the collected error data. The master policy module may determine a recovery action to be taken, based at least in part on the abstracted error data. The OS may also include an error collection routine that calls one or more specialized error handling modules in response to detecting a hardware error. The error collection routine may also retrieve information from firmware in response to detecting the hardware error. Other embodiments are described and claimed.

US Patent:

7971190, Jun 28, 2011

Filed:

Nov 30, 2006

Appl. No.:

11/606553

Inventors:

Bob Davies - Fremont CA, US
James Chapple - Chandler AZ, US
William K. Cheung - San Jose CA, US
Guoping Wen - Cupertino CA, US
Carolyn Dase - Chandler AZ, US
Dan Nowlin - Hillboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/44
G06F 11/30
G06F 15/18

US Classification:

717127, 717130, 717158, 714 47, 702186, 706 12

Abstract:

In general, in one aspect, the disclosure describes a method that includes interrupting a program running on a processor. The active instruction that was interrupted is identified. Event counts since a previous interrupt are harvested.

US Patent:

8627315, Jan 7, 2014

Filed:

Dec 31, 2004

Appl. No.:

10/555336

Inventors:

Shaofan Li - Shanghai, CN
Gao Haoyu - Shanghai, CN
William Cheung - San Jose CA, US
Ke Yu - Shanghai, CN

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/46
G06F 13/00
G06F 15/173

US Classification:

718100, 718104, 719324, 709224, 709226

Abstract:

A method and apparatus for cooperative guest firmware are described. In one embodiment, the method includes the launch of a virtual machine (VM) including a guest operating system (OS) and guest firmware. Prior to launching the VM, a data structure is generated in memory and is associated with the guest firmware to provide a virtualization policy provided by the VM as well as processor and platform configuration information to the guest firmware. In one embodiment, the guest firmware uses the data structure to access static information regarding the virtualization policy, as well as the processor and platform configuration information in response to requests from the guest OS. However, when the guest OS requires a host platform service, a virtual machine monitor (VMM) services the guest firmware requests for host platform services. Other embodiments are described and claimed.

US Patent:

20070005932, Jan 4, 2007

Filed:

Jun 29, 2005

Appl. No.:

11/169412

Inventors:

Douglas Covelli - Santa Clara CA, US
William Cheung - San Jose CA, US
Koichi Yamada - Los Gatos CA, US

International Classification:

G06F 12/00

US Classification:

711207000

Abstract:

Embodiments of memory management in a multiprocessor system are disclosed. Embodiments include a system and method for maintaining translation lookaside buffer (TLB) consistency or coherency in a multiprocessor system. A coalescing component receives from a host system a list of TLB pages to be invalidated or purged. The coalescing component uses information of the TLB invalidation broadcast mechanism in use by a processor in the multiprocessor system to evaluate the list of TLB pages. The coalescing component generates a single TLB invalidation message with a variable invalidation range to cover multiple TLB pages of the list or the entire list of TLB pages to be invalidated, and the invalidation message is used to invalidate multiple TLB pages on multiple processors of the host system. Other embodiments are described and claimed.