Wen Lan Chen

US Patent:

20190294785, Sep 26, 2019

Filed:

Mar 21, 2018

Appl. No.:

15/927484

Inventors:

- Austin TX, US
JAYANTA BHADRA - Austin TX, US
SANDIP RAY - Austin TX, US
WEN CHEN - Austin TX, US

International Classification:

G06F 21/55
G06N 99/00
G06N 5/04

Abstract:

A security system for vetting run-time operation of device hardware. A model stores vetted states based on device hardware security signals, a severity level value and at least one vetted next state. The vetting system compares each state of the device hardware with the vetted next states of a current state, and provides an indication and a severity level when the real next state does not match a vetted next state. In response to the indication, the synchronization system performs synchronization by comparing each subsequent real next state of the device hardware with the vetted states until initial synchronization occurs when any subsequent real next state matches a vetted state. The learning system receives feedback from the device hardware in response to the indication, and when indicated by the feedback, updates the model in accordance with the feedback.

US Patent:

20190250210, Aug 15, 2019

Filed:

Feb 9, 2018

Appl. No.:

15/893485

Inventors:

- Austin TX, US
Wen Chen - Austin TX, US
Jayanta Bhadra - Austin TX, US

Assignee:

NXP USA, Inc. - Austin TX

International Classification:

G01R 31/3187
G01R 31/317
G06F 11/27
G01R 31/3183

Abstract:

A method, system, and architecture () for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server () which receives specified hardware metric data () monitored at an integrated circuit device () in the field, identifies prioritized built-in self-test (BIST) fault detection tests () based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests () to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information () identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.

US Patent:

20180024614, Jan 25, 2018

Filed:

Jul 20, 2016

Appl. No.:

15/214599

Inventors:

- Austin TX, US
Wen Chen - Austin TX, US
Monica C. Farkash - Austin TX, US
Kuo-Kai Hsieh - Goleta CA, US

International Classification:

G06F 1/32

Abstract:

Self-configured, power-aware circuitry configured to enhance power efficiency within integrated circuitry by self-calibrating the power consumption utilized within the integrated circuitry according to the requirements of an application program running within the integrated circuitry. The power consumption is self-calibrated within the integrated circuitry on a per application-based manner so that the integrated circuitry can be implemented with a plurality of various generalized functionalities, each of which may or may not be utilized while a specific application program is running within the integrated circuitry. Power consumption within the integrated circuitry is reduced by independently and dynamically controlling multiple power sections delineated within the integrated circuitry.

Author:

Wen Jeng Chen

ISBN #:

0873394399