Wei Liu

Author:

Wei Liu

ISBN #:

0738494682

Author:

Wei Liu

ISBN #:

7532608522

Author:

Wei Liu

ISBN #:

7800877884

US Patent:

6380095, Apr 30, 2002

Filed:

Nov 16, 2000

Appl. No.:

09/716074

Inventors:

Wei Liu - Sunnyvale CA
Yiqiong Wang - Morgan Hill CA
Maocheng Li - Fremont CA
Anisul Khan - Sunnyvale CA
Dragan Podlesnik - Palo Alto CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438719, 438700, 438701, 438710, 438711

Abstract:

The present invention pertains to an etch chemistry and method useful for the etching of silicon surfaces. The method is particularly useful in the deep trench etching of silicon where profile control is important. In the case of deep trench etching, at least a portion of the substrate toward the bottom of the trench is etched using a combination of reactive gases including a fluorine-containing compound which does not contain silicon (FC); a silicon-containing compound (SC) which does not contain fluorine; and oxygen (O ).

US Patent:

6458671, Oct 1, 2002

Filed:

Feb 16, 2001

Appl. No.:

09/784997

Inventors:

Wei Liu - Sunnyvale CA
David Mui - San Jose CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

H01L 2120

US Classification:

438391, 438248, 438424, 438734

Abstract:

A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device. The method comprises: (1) providing a trench capacitor structure comprising (a) a silicon substrate having an upper and a lower surface; (b) first and second trenches extending from the upper surface into the silicon substrate; (c) first and second oxide regions lining at least portions of the first and second trenches; and (d) first and second polysilicon regions at least partially filling the oxide lined first and second trenches; and (2) forming a shallow trench from an upper surface of the structure, the shallow trench having a substantially flat trench bottom that forms an interface with portions of the silicon substrate, the first oxide region, the second oxide region, the first polysilicon region and the second polysilicon region, the shallow trench being formed by a process comprising (a) a first plasma etching step having an oxide:silicon:polysilicon selectivity of 1:1:1 and (b) a second plasma etching step having an oxide:silicon:polysilicon selectivity of 1:1:1, more preferably 1. 3:1:1.

US Patent:

6491835, Dec 10, 2002

Filed:

Dec 20, 1999

Appl. No.:

09/467560

Inventors:

Ajay Kumar - Sunnyvale CA
Anisul Khan - Sunnyvale CA
Wei Liu - Sunnyvale CA
John Chao - San Jose CA
Jeff Chinn - Foster City CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2100

US Classification:

216 51, 216 41, 216 79, 438717, 438719, 438736, 438738

Abstract:

The present disclosure provides a method for etching trenches, contact vias, or similar features to a depth of 100 m and greater while permitting control of the etch profile (the shape of the sidewalls surrounding the etched opening). The method requires the use of a metal-comprising masking material in combination with a fluorine-comprising plasma etchant. The byproduct produced by a combination of the metal with reactive fluorine species must be essentially non-volatile under etch process conditions, and sufficiently non-corrosive to features on the substrate being etched, that the substrate remains unharmed by the etch process. Although aluminum is a preferred metal for the metal-comprising mask, other metals can be used for the masking material, so long as they produce an essentially non-volatile, non-corrosive etch byproduct under etch process conditions. By way of example, and not by way of limitation, metallic materials recommended for the mask include aluminum, cadmium, copper, chromium, gallium, indium, iron, magnesium, manganese, nickel, and combinations thereof. In particular, aluminum in combination with copper or magnesium is particularly useful, where the copper or magnesium content is less than about 8% by weight, and other constituents total less than about 2% by weight.

US Patent:

6566270, May 20, 2003

Filed:

Sep 15, 2000

Appl. No.:

09/662677

Inventors:

Wei Liu - San Jose CA
Scott Williams - Sunnyvale CA
Stephen Yuen - Santa Clara CA
David Mui - San Jose CA
Meihua Shen - Fremont CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438706, 438714, 438719, 134 11, 134 12

Abstract:

A method for processing a substrate disposed in a substrate process chamber having a source power includes transferring the substrate into the substrate process chamber. A trench is etched on the substrate by exposing the substrate to a plasma formed from a first etchant gas by applying RF energy from the source power system and biasing the plasma toward the substrate. Byproducts adhering to inner surfaces of the substrate process chamber are removed by igniting a plasma formed from a second etchant gas including a halogen source in the substrate process chamber without applying bias power or applying minimal bias power. Thereafter, the substrate is removed from the chamber. At least 100 more substrates are processed with the etching-a-trench step and removing-etch-byproducts step before performing a dry clean or wet clean operation on the chamber.

US Patent:

6546339, Apr 8, 2003

Filed:

Jun 8, 2001

Appl. No.:

09/877133

Inventors:

Dimitri Bevc - Pleasanton CA
Wei Liu - San Jose CA
Alexander M. Popovici - Portola Valley CA

Assignee:

3D Geo Development, Inc. - Mountain View CA

International Classification:

G01V 128

US Classification:

702 18

Abstract:

Migration velocity analysis is performed using Angle-Domain Common Image Gathers (ACIGs). When the correct velocity model is employed for migration, all ACIG events corresponding to a subsurface location are aligned along a horizontal line. Residual moveout can be performed on each ACIG with a suite of trial residual velocity values, according to an angle-domain residual moveout equation. A best-fit residual velocity value that leads to horizontally-aligned events upon moveout can be selected by generating a distribution of semblance (amplitude summed over a given depth) over residual velocity. Best-fit residual velocity values corresponding to selected subsurface points can be employed to update the initial velocity model using a vertical update, normal ray update, or tomographic update method.

US Patent:

6589879, Jul 8, 2003

Filed:

Jan 18, 2001

Appl. No.:

09/766187

Inventors:

Scott M. Williams - Sunnyvale CA
Wei Liu - Sunnyvale CA
David Mui - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438714, 438719, 438723, 438724

Abstract:

A nitride etch process particularly useful when integrated with a silicon trench etch needing a sloping silicon surface adjacent to the interface between the silicon and an oxide layer intermediate the silicon and nitride. The nitride etch process is a plasma process having an etching gas mixture of sulfur hexafluoride (SF ) and trifluoromethane (CHF ) although nitrogen or oxygen may be added for additional controls. The trifluoromethane is believed to create a polymer passivation on the sidewalls of the hole being etched which, when the etch reaches the oxide-silicon interface, protects the interface and underlying silicon. The nitride etch may proceed through the oxide or a separate fluorocarbon-based oxide etching step may be performed before a bromine-based etch of the silicon starts.

US Patent:

6677242, Jan 13, 2004

Filed:

Aug 12, 2000

Appl. No.:

09/637838

Inventors:

Wei Liu - San Jose CA
Scott Williams - Sunnyvale CA
Stephen Yuen - Santa Clara CA
David Mui - San Jose CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438706, 438714, 438719, 134 11, 134 12

Abstract:

A method for processing a silicon substrate disposed in a substrate process chamber includes transferring the substrate into the substrate process chamber. The substrate having a hard mask formed thereon and a patterned photoresist overlying the hard mask to expose portions of the hard mask. The chamber being the type having a source power system and a bias power system. The method further includes etching the exposed portions of the hard mask to expose portions of the silicon substrate underlying the hard mask. Thereafter, the patterned photoresist is exposed to a first plasma formed from a first process gas to remove the photoresist from the hard mask. Thereafter, the exposed silicon substrate is etched by exposing the substrate to a second plasma formed from a second process gas by applying RF energy from the source power system and biasing the plasma toward the substrate. The substrate is transferred out of the substrate processing chamber.

US Patent:

6687618, Feb 3, 2004

Filed:

Aug 7, 2001

Appl. No.:

09/924123

Inventors:

Dimitri Bevc - Pleasanton CA
Alexander M. Popovici - Portola Valley CA
Wei Liu - San Jose CA

Assignee:

3D Geo Development, Inc. - Santa Clara CA

International Classification:

G01V 128

US Classification:

702 14, 702 18

Abstract:

A seismic velocity analysis method includes tying velocity parameter values such as residual velocity values to geological horizons (reflectors) within a seismic exploration volume. Common image gathers (CIGs) such a common reflection point (CRP) gathers or angle-domain common image gathers (ACIGs) are generated for a set of CIG grid points. Computed best-fit residual velocity values are then snapped to a neighboring horizon or vertically interpolated to the horizon, to generate residual velocity values along the horizon. The residual velocity values for points along the horizon are then selectively employed in updating the velocity model for the volume of interest.