Tong T Liu

US Patent:

6476636, Nov 5, 2002

Filed:

Sep 2, 2000

Appl. No.:

09/654240

Inventors:

Sheng Feng - Cupertino CA
Eddy C. Huang - San Jose CA
Chung-Yuan Sun - San Jose CA
Tong Liu - San Jose CA
Naihui Liao - Taipei, TW

Assignee:

Actel Corporation - Sunnyvale CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39, 326 38

Abstract:

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.

US Patent:

6611153, Aug 26, 2003

Filed:

Jan 31, 2002

Appl. No.:

10/061955

Inventors:

Sheng Feng - Cupertino CA
Eddy C. Huang - San Jose CA
Chung-Yuan Sun - San Jose CA
Tong Liu - San Jose CA
Naihui Liao - Taipei, TW

Assignee:

Actel Corporation - Sunnyvale CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38

Abstract:

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The routability of the regular routing structure is maximized by depositing switches according to designators. This novel designation method provides the same routability with approximately half the switches. Thus, further reduction in routing area is achieved.

US Patent:

6700404, Mar 2, 2004

Filed:

Jan 30, 2002

Appl. No.:

10/066398

Inventors:

Sheng Feng - Cupertino CA
Eddy C. Huang - San Jose CA
Chung-Yuan Sun - San Jose CA
Tong Liu - San Jose CA
Naihui Liao - Taipei, TW
Weidong Xiong - San Jose CA

Assignee:

Actel Corporation - Sunnyvale CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38, 326 39, 716 12, 716 14

Abstract:

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

US Patent:

6731133, May 4, 2004

Filed:

Feb 15, 2002

Appl. No.:

10/077190

Inventors:

Sheng Feng - Cupertino CA
Eddy C. Huang - San Jose CA
Chung-Yuan Sun - San Jose CA
Tong Liu - San Jose CA
Naihui Liao - Taipei, TW

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39, 326 38

Abstract:

A field-programmable gate array (FPGA), comprising: a first FPGA tile, the first FPGA tile comprising a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile. The first FPGA tile also comprising a secondary routing structure independent of the regular routing structure, coupled to each of the IGs, configured to transfer signals from said first FPGA tile to at least one other FPGA tile.

US Patent:

6744278, Jun 1, 2004

Filed:

Jan 31, 2002

Appl. No.:

10/061951

Inventors:

Tong Liu - San Jose CA
Sheng Feng - Cupertino CA
Eddy C. Huang - San Jose CA
Chung-Yuan Sun - San Jose CA
Naihui Liao - Taipei, TW

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39, 326 38

Abstract:

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

US Patent:

6774669, Aug 10, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/334338

Inventors:

Tong Liu - San Jose CA
Sheng Feng - Cupertino CA

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39, 326 40

Abstract:

The disclosed system relates to a freeway routing system and a fast-freeway routing system for a field programmable gate array. The field programmable gate array comprises a two by two array of field programmable gate array tiles. Each tile comprises: a plurality of functional groups arranged in rows and columns; a plurality of interface groups surrounding the plurality of functional groups such that one interface group is positioned at each end of each row and column, each of the interface groups comprising a set of freeway input and output ports; a freeway set of routing conductors configured to transfer signals to the freeway input ports and from the output ports of the interface groups in each of the field programmable gate array tiles. The freeway set of routing conductors comprises: a plurality of vertical conductors that form intersections with a plurality of horizontal conductors; and programmable bi-directional three state interconnect elements located at the intersections. The fast-freeway routing system comprises: a first group of fast-freeway routing conductors, a second group of fast-freeway routing conductors, a third group of fast-freeway routing conductors, and a fourth group of fast-freeway routing conductors.

US Patent:

6774670, Aug 10, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/334340

Inventors:

Sheng Feng - Cupertino CA
Tong Liu - San Jose CA

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39, 326 47

Abstract:

The invention relates to an intra-tile buffering system for a field programmable gate array. The field programmable gate array comprises a field programmable gate array tile comprising a number of rows and a number of columns. Each row has a left end and a right end, and each column has a top end and a bottom end. Each row comprises a plurality of functional groups with an interface group located at said right end and said left end. Each column comprises a plurality of functional groups with an interface group located at said top end and said bottom end. A primary routing structure is coupled to said functional groups and interface groups and configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive a primary input signal, perform a logic operation, and generate a primary output signal. Each interface group is configured to transfer signals from said primary routing structure to outside of said at least one field programmable gate array tile, and includes a plurality of input multiplexers configured to select signals received from outside of said at least one field programmable gate array tile and provide signals to the primary routing structure inside said at least one field programmable gate array tile.

US Patent:

6774672, Aug 10, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/334339

Inventors:

Sheng Feng - Cupertino CA
Tong Liu - San Jose CA

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19173

US Classification:

326 47, 326 39, 326 41

Abstract:

A field-programmable gate array (FPGA) is disclosed. A two-by-two array of FPGA tiles is surrounded by a JTAG interface, a Configuration interface and a BIST interface. Each interface is located adjacent to an outer edge of the two-by-two array of FPGA tiles. A plurality of boundary scan register chains are located adjacent to an outer perimeter of the two-by-two array of FPGA tiles and the JTAG, Configuration and BIST interfaces. A plurality of RAM blocks are located adjacent to an outer perimeter of the plurality of boundary register scan chains. A plurality of input/output pad rings is located adjacent to an outer perimeter of the plurality of ram blocks.

Author:

Tong Liu

ISBN #:

7508508068

Address:

5 Brockton, Irvine, CA 92620

Phone:

949 926-6775

VIN:

2HNYD2H28CH524564

Make:

ACURA

Model:

MDX

Year:

2012