Tomasz M Prokop

US Patent:

7894327, Feb 22, 2011

Filed:

Aug 23, 2005

Appl. No.:

11/209421

Inventors:

Tomasz Prokop - San Jose CA, US
Gongyu Zhou - North Epping, AU

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04B 7/216

US Classification:

370208, 370441

Abstract:

A method of generating a code sequence comprises populating at least one buffer with initial values based on a received spreading factor and desired code index; receiving a timing strobe; changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and outputting at least one code sequence value based on the values in the at least one buffer. An apparatus for generating a code sequence comprises means for populating at least one buffer with initial values based on a received spreading factor and desired code index; means for receiving a timing strobe; means for changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and means for outputting at least one code sequence value based on the values in the at least one buffer.

US Patent:

8462614, Jun 11, 2013

Filed:

Jan 19, 2011

Appl. No.:

13/009044

Inventors:

Tomasz Prokop - San Jose CA, US
Gongyu Zhou - North Epping, AU

Assignee:

Agere Systems LLC - Allentown PA

International Classification:

H04J 11/00
H04L 27/26

US Classification:

370208

Abstract:

In one embodiment, a buffer-based method for generating codes (such as Orthogonal Variable Spreading Factor (OVSF) codes) for spreading and despreading data, without using a chip-rate counter. First, a buffer is populated with initial values based on a received spreading factor and desired code index. Next, a timing strobe is received, and the values in the buffer are changed upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe. Finally, a code sequence value is generated based on the values in the buffer.

US Patent:

8559573, Oct 15, 2013

Filed:

Dec 27, 2005

Appl. No.:

11/318812

Inventors:

Rami Banna - Kensington, AU
Tomasz T. Prokop - San Jose CA, US
Long Ung - Marrickville, AU
Dominic Wing-Kin Yip - Carlingford, AU

Assignee:

Agere Systems LLC - Allentown PA

International Classification:

H04B 1/10

US Classification:

375350, 375229, 375232, 375316

Abstract:

A communications circuit includes a filter module with a sampling window, a control module, and an input buffer. The control module has a ray parameter interface to obtain information regarding significant ray changes that make it desirable to re-position the sampling window. The control module determines re-positioning parameters, responsive to this information, which reflect the re-positioning of the sampling window. The input buffer obtains samples of a received signal and outputs received signal data to the filter module. The filter module obtains the re-positioning parameters from the control module, and the filter module and control module temporally re-position the sampling window in duration and/or location in accordance with the re-positioning parameters, and output a filtered chip.

US Patent:

8582635, Nov 12, 2013

Filed:

Mar 2, 2012

Appl. No.:

13/410473

Inventors:

Tomasz Prokop - Pleasanton CA, US
Chaitanya Palusa - Fremont CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03H 7/30

US Classification:

375229, 375230, 375232, 375233, 375346, 375350, 455296, 455501, 370335, 370342, 333 18, 333 28 R, 708300, 327551

Abstract:

In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.

US Patent:

20070140320, Jun 21, 2007

Filed:

Dec 19, 2005

Appl. No.:

11/311003

Inventors:

Rami Banna - Kensington, AU
Adriel Kind - Macquarie Park, AU
Tomasz Prokop - San Jose CA, US
Dominic Yip - Carlingford, AU
Gongyu Zhou - North Epping, AU

International Classification:

H04B 1/00
H04B 1/10

US Classification:

375148000, 375350000

Abstract:

A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.

US Patent:

20130243066, Sep 19, 2013

Filed:

Mar 13, 2012

Appl. No.:

13/419009

Inventors:

Chaitanya Palusa - Fremont CA, US
Tomasz Prokop - Pleasanton CA, US
Adam B. Healey - Newburyport MA, US
Ye Liu - San Jose CA, US

International Classification:

H04L 27/01

US Classification:

375232

Abstract:

In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.

US Patent:

20150207648, Jul 23, 2015

Filed:

Feb 10, 2014

Appl. No.:

14/176728

Inventors:

- San Jose CA, US
Tomasz Prokop - Pleasanton CA, US
Hiep T. Pham - San Jose CA, US
Volodymyr Shvydun - Los Altos CA, US
Adam B. Healey - Newburyport MA, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

H04L 25/03
H04L 27/00
H04L 7/00

Abstract:

Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.

US Patent:

20140233668, Aug 21, 2014

Filed:

Apr 29, 2013

Appl. No.:

13/873003

Inventors:

- San Jose CA, US
Chaitanya Palusa - San Jose CA, US
Tomasz Prokop - San Jose CA, US
Adam Healey - Newburyport MA, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

H04L 27/12

US Classification:

375278, 375272

Abstract:

A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.

Author:

Tomasz Prokop

ISBN #:

8391504247