Timothy M Leonard

US Patent:

52396355, Aug 24, 1993

Filed:

Dec 10, 1991

Appl. No.:

7/807950

Inventors:

Robert E. Stewart - Stow MA
Timothy E. Leonard - Groton MA
Sherry T. Lee - Carlisle MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1208

US Classification:

395400

Abstract:

A method for translating a virtual address into a physical address, in which page tables used in the translation process are referenced by virtual addresses. Typically, a translation mechanism includes a translation buffer that, given a virtual address, can sometimes provide the corresponding physical address. A translation-buffer miss is said to occur when the translation buffer is presented with an address for which it can not provide the translation. When such a miss occurs, the translation mechanism obtains the translation by reading the page tables. When the translation mechanism attempts to read the page tables from virtual memory, a second-order miss can occur. The difficulty of infinite recursion of misses is avoided by handling second-order misses differently from first-order misses. When a second-order miss occurs, the translation mechanism uses a prototype page table entry and the virtual address of the page table entry to produce a physical address without using the page tables. Since consecutive pages of the page table in virtual memory reside in consecutive page frames in physical memory, a virtual address in the page tables can be translated to a physical address by adding the page frame number from the prototype page table entry to the virtual page number in the virtual address.

US Patent:

47870311, Nov 22, 1988

Filed:

Jan 4, 1985

Appl. No.:

6/688702

Inventors:

Paul A. Karger - Acton MA
Timothy E. Leonard - Groton MA
Andrew H. Mason - Nashua NH

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1214
G06F 944

US Classification:

364200

Abstract:

A computer system including a processor and memory, the processor having a virtual mode of operation in which it uses a virtual machine monitor which allows it to service a plurality of users contemporaneously in a multiplexed manner, and a non-virtual, or real, mode of operation. The computer system has a set of at least three operation mode protection rings representing a hierarchy of access privilege levels in both the real and virtual modes, with the number of privilege levels in both the real and virtual modes being the same. The privilege levels govern the accessibility of memory locations to programs and the executability of certain privileged instructions, which cause control to be transferred to the virtual machine monitor when the processor is in a virtual mode. The two most privileged levels in the virtual mode are both treated as corresponding to the second most privileged level in the real mode, whereby if the processor is in the most privileged virtual operating mode, access to memory locations is permitted only if the location is accessible to the second most privileged mode. When an instruction is retrieved, the processor first performs a probe operation to determine whether it can access any required memory locations in response to its current privilege level, and then determines whether it is in a privilege level which allows it to process the instruction.

US Patent:

58026045, Sep 1, 1998

Filed:

Jul 19, 1993

Appl. No.:

8/094651

Inventors:

Robert E. Stewart - Stow MA
Timothy Edwin Leonard - Groton MA
Sherry Tsi-chuan Lee - Carlisle MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1208

US Classification:

711206

Abstract:

A method for translating a virtual address into a physical address, in which page tables used in the translation process are referenced by virtual addresses. Typically, a translation mechanism includes a translation buffer that, given a virtual address, can sometimes provide the corresponding physical address. A translation-buffer miss is said to occur when the translation buffer is presented with an address for which it can not provide the translation. When such a miss occurs, the translation mechanism obtains the translation by reading the page tables. When the translation mechanism attempts to read the page tables from virtual memory, a second-order miss can occur. The difficulty of infinite recursion of misses is avoided by handling second-order misses differently from first-order misses. When a second-order miss occurs, the translation mechanism uses a prototype page table entry and the virtual address of the page table entry to produce a physical address without using the page tables. Since consecutive pages of the page table in virtual memory reside in consecutive page frames in physical memory, a virtual address in the page tables can be translated to a physical address by adding the page frame number from the prototype page table entry to the virtual page number in the virtual address.

US Patent:

20210341539, Nov 4, 2021

Filed:

Oct 21, 2019

Appl. No.:

17/285999

Inventors:

- Rockaway NJ, US
Timothy Joseph Leonard - East Greenwich RI, US

International Classification:

G01R 31/367
G06N 3/04
G06N 3/08
G01R 31/392

Abstract:

A computer-based system for automatically detecting when a battery changeout occurs has an input device, a neural net trained to identify when said battery changeout occurs based on data from a battery monitor and an output device. The system reads in battery data points once per a data period. The system then formats multiple data points into a data vector for the neural net. The neural net then produces an output vector indicating when a battery changeout occurs. The output vector may show a detected changeout as a step change in a graph.