Seungmoo K Choi

US Patent:

7563669, Jul 21, 2009

Filed:

May 16, 2006

Appl. No.:

11/383670

Inventors:

Sailesh Chittipeddi - Newport Beach CA, US
Seungmoo Choi - Macungie PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 21/8242
H01L 21/108

US Classification:

438243, 438239, 438242, 438245, 438386, 257301, 257302, 257E21651, 257E21653, 257E27092

Abstract:

An integrated circuit device having a capacitor structure. In one form of the invention, an integrated circuit device includes a capacitor structure formed along a surface of a semiconductor layer. The capacitor structure includes a region formed in the semiconductor surface, a layer of dielectric material formed along a trench wall of the trench region and a first layer of doped polysilicon formed over the layer of dielectric material in the trench region. The capacitor structure further includes a second layer of doped polysilicon formed over the first layer of polysilicon.

US Patent:

7989328, Aug 2, 2011

Filed:

Dec 19, 2006

Appl. No.:

11/641646

Inventors:

Seungmoo Choi - Newport Beach CA, US
Sameer Haddad - San Jose CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/38

US Classification:

438542, 438328, 257656, 257E29336, 257E21135

Abstract:

An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device-P-I-N diode structures.

US Patent:

20070099372, May 3, 2007

Filed:

Oct 31, 2006

Appl. No.:

11/590246

Inventors:

Sailesh Chittipeddi - Irvine CA, US
Seungmoo Choi - Newport Beach CA, US

International Classification:

H01L 21/8238
H01L 21/8242
H01L 29/788

US Classification:

438199000, 438243000, 257315000

Abstract:

An SOI device having SOI layers at two or more different depths below the surface of active regions of the device. Transistors for high-speed digital applications may be formed in the shallower active regions and RF power or high-voltage transistors may be formed in the deeper active regions. In one embodiment, the shallower active regions are fully-depleted while the deeper active regions are partially-depleted.

US Patent:

20090067213, Mar 12, 2009

Filed:

Sep 6, 2007

Appl. No.:

11/899597

Inventors:

Matthew Buynoski - Palo Alto CA, US
Seungmoo Choi - Newport Beach CA, US
Chakravarthy Gopalan - Santa Clara CA, US
Dongxiang Liao - Sunnyvale CA, US
Christie Marrian - San Jose CA, US

International Classification:

G11C 11/00
B05D 5/12

US Classification:

365148, 4271263

Abstract:

In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.

US Patent:

20110253968, Oct 20, 2011

Filed:

Jun 21, 2011

Appl. No.:

13/165652

Inventors:

Seungmoo CHOI - Newport Beach CA, US
Sameer HADDAD - San Jose CA, US

International Classification:

H01L 29/868
H01L 21/02
H01L 45/00
H01L 21/329

US Classification:

257 5, 438542, 438382, 257656, 257E29336, 257E45001, 257E21002, 257E21352

Abstract:

An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device—P-I-N diode structures.

US Patent:

20160380195, Dec 29, 2016

Filed:

Sep 7, 2016

Appl. No.:

15/258234

Inventors:

- San Jose CA, US
Seungmoo Choi - Newport Beach CA, US
Chakravarthy Gopalan - Santa Clara CA, US
Dongxiang Liao - Sunnyvale CA, US
Christie Marrian - San Jose CA, US

International Classification:

H01L 45/00

Abstract:

In fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode, the oxide layer comprising an oxygen deficiency and/or defects therein. A second electrode is then provided on the oxide layer.

US Patent:

20150144857, May 28, 2015

Filed:

Feb 2, 2015

Appl. No.:

14/612083

Inventors:

- Sunnyvale CA, US
Seungmoo CHOI - Newport Beach CA, US
Chakravarthy GOPALAN - Santa Clara CA, US
Dongxiang LIAO - Sunnyvale CA, US
Christie MARRIAN - San Jose CA, US

International Classification:

H01L 45/00

US Classification:

257 2, 438104

Abstract:

In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is the formed on the layer.