David Mun Choi

US Patent:

8116225, Feb 14, 2012

Filed:

Oct 16, 2009

Appl. No.:

12/581018

Inventors:

Kanapathipillai Ketheesan - San Francisco CA, US
David Choi - Cupertino CA, US

Assignee:

Venturi Wireless - Sunnyvale CA

International Classification:

H04L 12/26

US Classification:

370252, 709224, 709233

Abstract:

A bandwidth estimation algorithm detects peaks and/or average per-user bandwidth of data communication networks, such as narrowband and broadband wide-area radio access networks. Estimation can be performed at the TCP/IP layer with no lower layer (PHY, MAC, etc. ) information assumed to be available. However, the bandwidth estimation algorithm can be applied to anywhere bandwidth needs to be estimated as well.

US Patent:

8351358, Jan 8, 2013

Filed:

Dec 7, 2009

Appl. No.:

12/632700

Inventors:

Kanapathipillai Ketheesan - San Francisco CA, US
Krishna Ramadas - Cupertino CA, US
Chico Jayanthan - San Ramon CA, US
David Choi - Cupertino CA, US

Assignee:

Venturi Wireless, Inc. - Sunnyvale CA

International Classification:

H04B 7/00

US Classification:

370310

Abstract:

A system for optimizing communications on a radio network by altering transitions between different link states that includes several modules. The activity, environment, and load module monitor monitors the link layer based on spectral-load metrics and radio-link metrics. The state transition control module determines when user equipment transitions between different states based on the type of user equipment, user equipment battery life, whether the user equipment is connected to an alternating current outlet, a spectral cost, and a backhaul cost. The channel state influencer module uses any of direct messages, ping messages, and keep-alive messages to influence the link state. The policy and preference handler enables or disables transitions based on the bearer technology type, the type of user equipment, the user's subscription plan, and the load level on the network.

US Patent:

20060193174, Aug 31, 2006

Filed:

Feb 25, 2005

Appl. No.:

11/067313

Inventors:

David Choi - Cupertino CA, US
Eui Kwon - San Jose CA, US
Kyu Choi - Cupertino CA, US

Assignee:

O2IC - Santa Clara CA

International Classification:

G11C 11/34
G11C 14/00

US Classification:

365185080

Abstract:

A memory cell structure includes non-volatile as well as SRAM memory cells that share the same bitline and operate differentially. The SRAM cell includes first and second MOS transistors that are coupled to the same true and complementary bit lines that the non-volatile memory cells are coupled to. The non-volatile memory cells are erased prior to being programmed. Programming of the non-volatile memory cells may be carried out via hot-electron injection or Fowler-Nordheim tunneling. Data stored in the non-volatile memory cells may be transferred to the SRAM cell. The differential reading and writing of data reduces over-erase of the non-volatile devices.

US Patent:

20060227605, Oct 12, 2006

Filed:

Jan 3, 2006

Appl. No.:

11/325224

Inventors:

David Choi - Cupertino CA, US
John Villasenor - San Francisco CA, US

International Classification:

G11C 14/00

US Classification:

365185080

Abstract:

Architectures are described that can include integrated non-volatile memory modules. Integrated non-volatile memory modules are a form of memory that is integrated on a single chip and includes at least one volatile memory cell and at least one non-volatile memory device. Information can be loaded between the at least one memory cell and the at least one non-volatile memory device in coordination with the supply of power to the integrated non-volatile memory device. In many embodiments, the supply of power to the integrated non-volatile memory device and the loading of information between the volatile memory cells and non-volatile memory devices are controlled to conserve energy. One embodiment of the present invention includes processing circuitry connected to an integrated non-volatile memory module and a power supply connected to the processing circuitry and integrated non-volatile memory module. In addition, the integrated non-volatile memory module is integrated on a single chip and includes at least one volatile memory cell that is connected to at least one non-volatile memory device.

US Patent:

20070242514, Oct 18, 2007

Filed:

Mar 10, 2006

Appl. No.:

11/373818

Inventors:

David Choi - Cupertino CA, US
Kyu Choi - Cupertino CA, US

Assignee:

O2IC, Inc. - Santa Clara CA

International Classification:

G11C 11/34

US Classification:

365185170

Abstract:

A multitude of NAND flash memory cells coupled to a bit line of a NAND flash memory array includes, in part, a highly doped source region coupled to a first terminal and a highly doped drain region coupled to a second terminal of the multitude of cells. Each NAND memory cell includes, in part, a first gate layer and a second gate layer both adapted to receive a voltage. The second gate layers of the NAND flash memory cells are connected to one another.

US Patent:

20080061355, Mar 13, 2008

Filed:

Mar 1, 2007

Appl. No.:

11/713780

Inventors:

David Choi - Cupertino CA, US

Assignee:

Embedded Memory, Inc. - Cupertino CA
Ace Memory, Inc. - Santa Clara CA

International Classification:

H01L 29/788
H01L 21/336

US Classification:

257316000, 438266000, 257E29300, 257E21422

Abstract:

In accordance with the present invention, a new method, its structure and manufacturing method is described to reduce memory cell size about the half of the conventional method for a non-volatile NAND Flash cell. The control gates in a string of the NAND Flash cell array is formed as the combination of the drawn control gate and the self-aligned control gate by using a spacer method. The source and drain of a NAND cell is defined as the low doped region underneath the spacer.

US Patent:

20080061358, Mar 13, 2008

Filed:

Mar 1, 2007

Appl. No.:

11/713548

Inventors:

David Choi - Cupertino CA, US

Assignee:

Embedded Memory, Inc. - Santa Clara CA

International Classification:

H01L 27/108
H01L 21/8242

US Classification:

257319000, 438266000, 257E27084, 257E21646

Abstract:

In accordance with the present invention, a new method, its structure and manufacturing method is proposed to reduce memory cell size about the half of the conventional method for a non-volatile NAND Flash cell. The control gates in a string of the NAND Flash cell array is formed as the combination of the drawn control gate and the self-aligned control gate by using a spacer method. The source and drain of a NAND cell is defined as the low doped region underneath the spacer.

US Patent:

20120106385, May 3, 2012

Filed:

Jan 6, 2012

Appl. No.:

13/345550

Inventors:

Kanapathipillai KETHEESAN - San Francisco CA, US
David Choi - Cupertino CA, US

International Classification:

H04W 24/02

US Classification:

370252

Abstract:

A bandwidth estimation algorithm on shared links detects peaks and/or average per-user bandwidth. Estimating is performed at the transport or IP layer with no assistance from lower layer (PHY, MAC, etc.) and the techniques can be used for any of adjusting the level of video optimization to the available bandwidth; driving QoS decisions at the transmitter based on available bandwidth; improving QoS enforcement during transitions among hybrid technologies on a wireless links; and correcting estimates on devices delivering bursty payload.