Sathyanandan Rajivan

US Patent:

62821466, Aug 28, 2001

Filed:

Jun 21, 1999

Appl. No.:

9/336939

Inventors:

Frank Tzen-Wen Guo - Danville CA
Sathyanandan Rajivan - San Jose CA
Yat Fai Lam - Milpitas CA
Tzu-Chien Hung - Cupertino CA

Assignee:

Rise Technology, Inc. - Santa Clara CA

International Classification:

G11C 800

US Classification:

36523006

Abstract:

The present invention discloses a voltage shifter capable of interfacing between two circuitry each is operating in different voltage range. The voltage shifter comprises an input buffer for converting an external input signal switching within a high voltage range to an internal input signal switching within a low voltage range, an output driver for converting an internal output signal switching within the low voltage range to an external output signal switching within the high voltage range; and a reference voltage generator for generating a reference voltage to the input buffer and the output driver. In addition, the voltage shifter is designed such that each of the transistors within is protected against voltage breakdown so that the voltage shifter can be built by transistors using the low voltage process.

US Patent:

61572365, Dec 5, 2000

Filed:

Sep 11, 1997

Appl. No.:

8/927237

Inventors:

Sathyanandan Rajivan - San Jose CA
Raoul B. Salem - Redwood City CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H03H 1126

US Classification:

327276

Abstract:

The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit.

US Patent:

61408565, Oct 31, 2000

Filed:

Sep 11, 1997

Appl. No.:

8/956624

Inventors:

Sathyanandan Rajivan - San Jose CA
Raoul B. Salem - Redwood City CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H03H 1126

US Classification:

327276

Abstract:

The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit.

US Patent:

55286380, Jun 18, 1996

Filed:

May 24, 1995

Appl. No.:

8/449355

Inventors:

Sathyanandan Rajivan - San Jose CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

H03D 324

US Classification:

375376

Abstract:

An inventive apparatus for generating a plurality of phase-shifted clocks on an IC, including a PLL disposed at a first location for generating a reference clock and a reference voltage, local clock generation circuit disposed at a second location, and a first conductor coupling to both the PLL and the local clock generation circuit for furnishing the reference clock from the PLL to the local clock generation circuit. The inventive apparatus further includes a second conductor coupling to both the PLL and the local clock generation circuit for furnishing the reference voltage from the PLL to the local clock generation circuit; wherein the plurality of phase-shifted clocks are generated at the second location, responsive to the reference voltage and the reference clock, using the local clock generation circuit.

US Patent:

55415369, Jul 30, 1996

Filed:

May 24, 1995

Appl. No.:

8/448886

Inventors:

Sathyanandan Rajivan - San Jose CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

H03K 19096

US Classification:

326 98

Abstract:

A circuit for evaluating logic inputs responsive to a reference clock, which circuit includes a first clock terminal for coupling with a first clock, the first clock being delayed from the reference clock by a first frequency dependent delay period. The circuit includes a second clock terminal for coupling with a second clock, the second clock being delayed from the reference clock by a second frequency dependent delay period. The inventive circuit further includes a first circuit stage, which includes a pulse generation circuit coupled to both the first clock terminal and the second clock terminal. In one embodiment, the first circuit stage further includes an output terminal, an evaluation device coupled to the output terminal and the pulse generation circuit. The first circuit stage also includes a precharge device coupled to the output terminal, a third clock terminal, and a first logic level, the third clock being delayed from the reference clock by a third frequency dependent delay period.

US Patent:

59735414, Oct 26, 1999

Filed:

Sep 11, 1997

Appl. No.:

8/927976

Inventors:

Sathyanandan Rajivan - San Jose CA
Raoul B. Salem - Redwood City CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H03K 1704

US Classification:

327374

Abstract:

The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit.

US Patent:

55326250, Jul 2, 1996

Filed:

Mar 1, 1995

Appl. No.:

8/397419

Inventors:

Sathyanandan Rajivan - San Jose CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

H03K 19017

US Classification:

326 98

Abstract:

A wave propagation circuit having one or more circuit stages. Each circuit stage preferably has the same number of evaluation devices as the number of logic inputs into that circuit stage. The circuit stages alternately precharge and evaluate in a serial, wavelike manner responsive to a clock signal. During the precharge cycle of the clock, a precharge pulse propagates from circuit stage to circuit stage to precharge the output nodes of the circuit stages in a distributed, serial manner. During the evaluation cycle of the clock, a pulsed data signal permits the first stage to evaluate its inputs. Responsive to the output of the first circuit stage, a second circuit stage evaluates its inputs. The circuit further includes forward conduction devices and feedback devices to improve the noise margin and to reduce output errors caused by charge sharing and charge redistribution. Optional power saving circuits precharge an output terminal of a circuit stage during a precharge phase only if that output terminal switches during a previous evaluation phase.

US Patent:

57291586, Mar 17, 1998

Filed:

Jul 7, 1995

Appl. No.:

8/499716

Inventors:

Sathyanandan Rajivan - San Jose CA
Raoul B. Salem - Redwood City CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H03K 190175

US Classification:

326 87

Abstract:

The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit.