Ruben Castelino
from Apex, NC
Ruben Castelino Phones & Addresses
- 1940 Mostyn Ln, Apex, NC 27502 • 919 267-5041
Work
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Company:QualcommFeb 1, 2014 to Feb 2019
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Position:Hardware design engineer
Education
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Degree:Bachelors, Bachelor of Science
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School / High School:University of Cincinnati1984 to 1988
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Specialities:Electronics Engineering
Skills
Debugging • Logic Synthesis • Hardware Architecture • Static Timing Analysis • Simulations • Verilog • Formal Verification • Spice • Perl • Cmos • Place and Route • Analog • Physical Design • Rtl Design • Semiconductors • Asic • Digital Circuit Design • C • Unix • Microprocessors • Schematic Capture • Circuit Analysis • Computer Architecture • Vlsi • Timing Closure • Custom Digital Circuit Design • Creative Problem Solving • Logic Design • Processors • Hardware • Functional Verification • Fpga • Soc • Systemverilog • Ic • Tcl • Signal Integrity • Low Power Design • Circuit Design • Standard Cell Digital Circuit Design • Rtl Coding and Debug • Timing Analysis • Circuit Simulation
Industries
Semiconductors
Resumes
Staff Physical Design Engineer
view sourceLocation:
1940 Mostyn Ln, Apex, NC 27502
Industry:
Semiconductors
Work:
Qualcomm Feb 1, 2014 - Feb 2019
Hardware Design Engineer
Marvell Semiconductor Feb 1, 2014 - Feb 2019
Staff Physical Design Engineer
Amd Dec 2012 - Dec 2013
Hardware Design Engineer
Computer Hardware and Design Engineering Dec 2012 - Dec 2013
Senior Hardware Design Engineer
Intel Corporation Apr 2003 - Feb 2012
Component Design Engineer
Hardware Design Engineer
Marvell Semiconductor Feb 1, 2014 - Feb 2019
Staff Physical Design Engineer
Amd Dec 2012 - Dec 2013
Hardware Design Engineer
Computer Hardware and Design Engineering Dec 2012 - Dec 2013
Senior Hardware Design Engineer
Intel Corporation Apr 2003 - Feb 2012
Component Design Engineer
Education:
University of Cincinnati 1984 - 1988
Bachelors, Bachelor of Science, Electronics Engineering St Xavier High School 1980 - 1984
Bachelors, Bachelor of Science, Electronics Engineering St Xavier High School 1980 - 1984
Skills:
Debugging
Logic Synthesis
Hardware Architecture
Static Timing Analysis
Simulations
Verilog
Formal Verification
Spice
Perl
Cmos
Place and Route
Analog
Physical Design
Rtl Design
Semiconductors
Asic
Digital Circuit Design
C
Unix
Microprocessors
Schematic Capture
Circuit Analysis
Computer Architecture
Vlsi
Timing Closure
Custom Digital Circuit Design
Creative Problem Solving
Logic Design
Processors
Hardware
Functional Verification
Fpga
Soc
Systemverilog
Ic
Tcl
Signal Integrity
Low Power Design
Circuit Design
Standard Cell Digital Circuit Design
Rtl Coding and Debug
Timing Analysis
Circuit Simulation
Logic Synthesis
Hardware Architecture
Static Timing Analysis
Simulations
Verilog
Formal Verification
Spice
Perl
Cmos
Place and Route
Analog
Physical Design
Rtl Design
Semiconductors
Asic
Digital Circuit Design
C
Unix
Microprocessors
Schematic Capture
Circuit Analysis
Computer Architecture
Vlsi
Timing Closure
Custom Digital Circuit Design
Creative Problem Solving
Logic Design
Processors
Hardware
Functional Verification
Fpga
Soc
Systemverilog
Ic
Tcl
Signal Integrity
Low Power Design
Circuit Design
Standard Cell Digital Circuit Design
Rtl Coding and Debug
Timing Analysis
Circuit Simulation
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