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Ruben S Castelino

age ~58

from Apex, NC

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Also known as:
  • Ruben William Castelino
  • Ruben W Castelino
  • Ruben W Castelijn
  • Ruben O
Phone and address:
1940 Mostyn Ln, Apex, NC 27502
919 267-5041
Related to:
Connected to:

Ruben Castelino Phones & Addresses

  • 1940 Mostyn Ln, Apex, NC 27502 • 919 267-5041
  • Cary, NC
  • 57 Blanchette Dr, Marlborough, MA 01752 • 508 460-3853
  • 8 Royal Crest Dr, Marlborough, MA 01752 • 508 460-3853
  • 1 Hammond Cir, Hudson, MA 01749 • 978 212-5546
  • Stow, MA
  • Worcester, MA

Work

  • Company:
    Qualcomm
    Feb 1, 2014 to Feb 2019
  • Position:
    Hardware design engineer

Education

  • Degree:
    Bachelors, Bachelor of Science
  • School / High School:
    University of Cincinnati
    1984 to 1988
  • Specialities:
    Electronics Engineering

Skills

Debugging • Logic Synthesis • Hardware Architecture • Static Timing Analysis • Simulations • Verilog • Formal Verification • Spice • Perl • Cmos • Place and Route • Analog • Physical Design • Rtl Design • Semiconductors • Asic • Digital Circuit Design • C • Unix • Microprocessors • Schematic Capture • Circuit Analysis • Computer Architecture • Vlsi • Timing Closure • Custom Digital Circuit Design • Creative Problem Solving • Logic Design • Processors • Hardware • Functional Verification • Fpga • Soc • Systemverilog • Ic • Tcl • Signal Integrity • Low Power Design • Circuit Design • Standard Cell Digital Circuit Design • Rtl Coding and Debug • Timing Analysis • Circuit Simulation

Industries

Semiconductors

Us Patents

  • Position Reference Beacon For Integrated Circuits

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  • US Patent:
    20050094866, May 5, 2005
  • Filed:
    Nov 3, 2003
  • Appl. No.:
    10/700183
  • Inventors:
    Ruben Castelino - Marlborough MA, US
    John Kowaleski - Princeton MA, US
  • International Classification:
    G06K009/00
  • US Classification:
    382149000, 382145000
  • Abstract:
    A beacon for providing a reference location on an integrated circuit is disclosed. The beacon comprises a device capable of emitting radiation and disposed at a corresponding reference location on the integrated circuit, wherein the device is capable of being controlled independent of integrated circuit operations.

  • Autonomous Pipeline Reconfiguration For Continuous Error Correction For Fills From Tertiary Cache Or Memory

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  • US Patent:
    56300557, May 13, 1997
  • Filed:
    May 5, 1995
  • Appl. No.:
    8/437111
  • Inventors:
    Peter J. Bannon - Concord MA
    Ruben W. Castelino - Marlboro MA
    Chandrasekhara Somanathan - Milpitas CA
  • Assignee:
    Digital Equipment Corporation - Maynard MA
  • International Classification:
    H03M 1300
    G06F 1100
  • US Classification:
    39518505
  • Abstract:
    A computer system includes a central processing unit which further includes an execution unit and two levels of data cache and an error checking and correcting unit. During error-free operation, external cache fill data is supplied directly to the execution unit while a copy of the data is checked by the error checking and correcting unit. In response to detection of an error by the error checking and correcting unit, the use of the fill data by the execution unit is aborted. Furthermore, the data path for fill data is dynamically reconfigured to force remaining pending fill data to pass through the error checking and correcting unit prior to reaching the execution unit or either of the caches. Once all pending fill data has been processed, the data path is reconfigured back to its error-free mode of operation such that fill data is transmitted directly to the execution unit while a copy of the data is checked by the error checking an correcting unit.

Resumes

Ruben Castelino Photo 1

Staff Physical Design Engineer

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Location:
1940 Mostyn Ln, Apex, NC 27502
Industry:
Semiconductors
Work:
Qualcomm Feb 1, 2014 - Feb 2019
Hardware Design Engineer
Marvell Semiconductor Feb 1, 2014 - Feb 2019
Staff Physical Design Engineer
Amd Dec 2012 - Dec 2013
Hardware Design Engineer
Computer Hardware and Design Engineering Dec 2012 - Dec 2013
Senior Hardware Design Engineer
Intel Corporation Apr 2003 - Feb 2012
Component Design Engineer
Education:
University of Cincinnati 1984 - 1988
Bachelors, Bachelor of Science, Electronics Engineering St Xavier High School 1980 - 1984
Skills:
Debugging
Logic Synthesis
Hardware Architecture
Static Timing Analysis
Simulations
Verilog
Formal Verification
Spice
Perl
Cmos
Place and Route
Analog
Physical Design
Rtl Design
Semiconductors
Asic
Digital Circuit Design
C
Unix
Microprocessors
Schematic Capture
Circuit Analysis
Computer Architecture
Vlsi
Timing Closure
Custom Digital Circuit Design
Creative Problem Solving
Logic Design
Processors
Hardware
Functional Verification
Fpga
Soc
Systemverilog
Ic
Tcl
Signal Integrity
Low Power Design
Circuit Design
Standard Cell Digital Circuit Design
Rtl Coding and Debug
Timing Analysis
Circuit Simulation

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Ruben Castelino

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Ruben Castelino

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