Rajendra D Pendse

US Patent:

6417573, Jul 9, 2002

Filed:

Mar 20, 2000

Appl. No.:

09/531547

Inventors:

Rajendra D. Pendse - Fremont CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H01L 2940

US Classification:

257778, 257782

Abstract:

A fluxing composition is disclosed. The composition comprises a high molecular weight carboxylic acid that forms a combination of carboxylate salts and unreacted acid anhydrides when applied to a solder alloy and exposed to temperatures in the range of about 150 to 350Â C. in an inert atmosphere and a carrier fluid comprising a mixture of organic solvents that is heat stable and non-reactive with the solder alloy and has a high viscosity at room temperature. Also disclosed is an integrated circuit assembly comprising an integrated circuit comprising a chip attached to a substrate by a plurality of solder joints and a thin layer of a residue comprising the carboxylate salts and acid anhydride. The film of residue is formed concomitantly with the formation of the solder joints during the reflow cycle. Since the residue is reactive with an epoxy used in bonding the chip to the substrate, the usual process step of cleaning the flux residue prior to dispensing the epoxy is obviated.

US Patent:

6737295, May 18, 2004

Filed:

Feb 22, 2002

Appl. No.:

10/081491

Inventors:

Rajendra Pendse - Fremont CA
Nazir Ahmad - San Jose CA
Andrea Chen - San Jose CA
Kyung-Moon Kim - Ichon-si, KR
Young Do Kweon - Cupertino CA
Samuel Tam - Daly City CA

Assignee:

ChipPAC, Inc. - Fremont CA

International Classification:

H01L 2144

US Classification:

438106, 438108, 257778

Abstract:

A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material nor any melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries. In another aspect, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern in relation to the positions of the second level interconnections between the package and the printed circuit board.

US Patent:

6780682, Aug 24, 2004

Filed:

Feb 22, 2002

Appl. No.:

10/081425

Inventors:

Rajendra Pendse - Fremont CA

Assignee:

ChipPAC, Inc. - Fremont CA

International Classification:

H01L 2148

US Classification:

438127, 438108

Abstract:

A method for encapsulating flip chip interconnects includes applying a limited quantity of encapsulating resin to the interconnect side of an integrated circuit chip, and thereafter bringing the chip together with a substrate under conditions that promote the bonding of bumps on the interconnect side of the chip with bonding pads on the substrate. In some embodiments, the step of applying resin to the chip includes dipping the interconnect side of the chip to a predetermined depth in a pool of resin, and then withdrawing the chip from the resin pool. In some embodiments the step of applying resin to the chip includes providing a reservoir having a bottom, providing a pool of resin in the reservoir to a shallow depth over the reservoir bottom, dipping the chip into the resin pool so that the bumps contact the reservoir bottom, and then withdrawing the chip from the resin pool. Also, apparatus for applying a precise volume of encapsulating resin to a chip, includes a reservoir having a bottom, and means for dispensing a pool of encapsulating resin to a predetermined depth over the reservoir bottom.

US Patent:

6815252, Nov 9, 2004

Filed:

Mar 9, 2001

Appl. No.:

09/802664

Inventors:

Rajendra D. Pendse - Fremont CA

Assignee:

ChipPAC, Inc. - Fremont CA

International Classification:

H01L 2144

US Classification:

438107, 438108, 438118, 438455, 438612, 438613

Abstract:

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

US Patent:

6828220, Dec 7, 2004

Filed:

Mar 9, 2001

Appl. No.:

09/802443

Inventors:

Rajendra D. Pendse - Fremont CA
Marcos Karnezos - Palo Alto CA

Assignee:

ChipPAC, Inc. - Fremont CA

International Classification:

H01L 2144

US Classification:

438612, 438613, 438616, 257620, 257626, 257735, 257786

Abstract:

A method for connecting a chip to a leadframe includes forming bumps on a die by a Au stud-bumping technique, and attaching the chip to the leadframe by thermo-compression of the bumps onto bonding fingers of the leadframe. Also a flip chip-in-leadframe package is made according to the method. The package provides improved electrical performance particularly for devices used in RF applications.

US Patent:

6940178, Sep 6, 2005

Filed:

Feb 22, 2002

Appl. No.:

10/080384

Inventors:

Young-Do Kweon - Pleasanton CA, US
Rajendra Pendse - Fremont CA, US
Nazir Ahmad - San Jose CA, US
Kyung-Moon Kim - Ichon-si, KR

Assignee:

ChipPAC, Inc. - Fremont CA

International Classification:

H01L023/48

US Classification:

257780, 257737, 257778, 257738, 257779

Abstract:

A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool. Also, a method for forming an interconnect between a first member and a second member of an electronic package includes providing one of the members with the stud bumps of the invention and then bringing the corresponding bumps and pads together in a bonding process, the compliance of the stems portions of the bumps accommodating the variance from coplanarity of the pad surfaces.

US Patent:

7033859, Apr 25, 2006

Filed:

May 20, 2004

Appl. No.:

10/850093

Inventors:

Rajendra D. Pendse - Fremont CA, US

Assignee:

ChipPAC, Inc. - Fremont CA

International Classification:

H01L 21/44
H01L 21/30

US Classification:

438107, 438108, 438118, 438455

Abstract:

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

US Patent:

7034391, Apr 25, 2006

Filed:

Nov 8, 2004

Appl. No.:

10/983898

Inventors:

Rajendra D. Pendse - Fremont CA, US

Assignee:

ChipPAC, Inc. - Fremont CA

International Classification:

H01L 23/28
H01L 23/52
H01L 21/48
H05K 7/00

US Classification:

257691, 257778, 257787, 438111, 361735, 361760

Abstract:

A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.