Hari Pendurty

US Patent:

8539290, Sep 17, 2013

Filed:

Feb 5, 2013

Appl. No.:

13/759667

Inventors:

Hari Pendurty - Pearland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/28

US Classification:

714724, 714718

Abstract:

An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.

US Patent:

20110096820, Apr 28, 2011

Filed:

Oct 27, 2010

Appl. No.:

12/913643

Inventors:

Kevin Patrick Lavery - Sugarland TX, US
Hari Pendurty - Pearland TX, US

International Classification:

H04B 17/00

US Classification:

375224

Abstract:

A modulation evaluation system associated with frequency modulations periods of a phase-locked loop is described. The system includes a first accumulator for accumulating clock edges a window of the frequency modulation periods; a second accumulator coupled to the first accumulator and operative for accumulating clock edges during whole periods of the frequency modulation periods; a dynamic enable control coupled to a first input associated with the first accumulator and a second input associated with the second accumulator, wherein the dynamic enable control selectively transmits a first enable signal that controls when the first accumulator accumulates clock edges and a second enable signal controls when the second accumulator accumulates clock edges, and accumulating clock edges enable modulation evaluation during production.

US Patent:

20120072790, Mar 22, 2012

Filed:

Sep 16, 2010

Appl. No.:

12/884148

Inventors:

Hari Pendurty - Pearland TX, US

International Classification:

G11C 29/04
G11C 7/10
G06F 11/22
G11C 29/48

US Classification:

714718, 365201, 36518902, 714E11145

Abstract:

An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.

US Patent:

20130322176, Dec 5, 2013

Filed:

Aug 9, 2013

Appl. No.:

13/963697

Inventors:

Hari Pendurty - Pearland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 29/00

US Classification:

36518511

Abstract:

An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.