Poongovan Ponnavaikko

US Patent:

20170199760, Jul 13, 2017

Filed:

Mar 28, 2017

Appl. No.:

15/471991

Inventors:

- San Jose CA, US
Poongovan Ponnavaikko - Santa Clara CA, US
Babu Neelam - Santa Clara CA, US

International Classification:

G06F 9/46
G06F 3/06
G06F 11/14

Abstract:

Techniques are disclosed for generating a multi-transactional system using transactional memory techniques. According to certain embodiments, a device may include a memory, one or more processing entities, and a transactional memory system for maintaining a plurality of transactional memory (TM) logs in a first portion of the memory. Each TM log may be associated with one transaction from a plurality of transactions sequentially executed by the one or more processing entities and each transaction comprises a plurality of operations. Furthermore, each TM log associated with each transaction comprises information associated with changes to a second portion of the memory caused by execution of operations from the transaction using the one or more processing entities. The TM logs for completed transactions may be used for error detection and recovery and maintaining high availability of the device.

US Patent:

20160182241, Jun 23, 2016

Filed:

Oct 26, 2015

Appl. No.:

14/923327

Inventors:

- San Jose CA, US
Dan N. Retter - Cupertino CA, US
Mayur Mahajan - San Francisco CA, US
Poongovan Ponnavaikko - Santa Clara CA, US

International Classification:

H04L 12/18
H04L 12/721

Abstract:

Certain embodiments of the present invention provide techniques that enable messages to be sent to a processing entity within a computing device without knowing the network address of the processing entity. In certain embodiments, instead of using the network address of the processing entity, a message can be communicated to the processing entity using information indicative of a role or state or function performed by the processing entity.

US Patent:

20150081986, Mar 19, 2015

Filed:

Jul 11, 2014

Appl. No.:

14/329767

Inventors:

- San Jose CA, US
Poongovan Ponnavaikko - Santa Clara CA, US
Babu Neelam - Santa Clara CA, US

International Classification:

G06F 9/46
G06F 12/02

US Classification:

711154

Abstract:

Techniques are provided for reliable and efficient access to non-transactional resources using transactional memory. In certain aspects, a device may include memory and one or more processing entities, configurable to execute a first transaction comprising one or more write operations to a first memory address, and a second transaction comprising one or more write operations to a second memory address. The first memory address and the second memory address may be mapped to the same controller for a hardware component and the one or more processing entities may commence execution of the second transaction after the first transaction starts execution and before the completion of the first transaction. The device may also include a transactional memory system configurable to communicate data written to the first memory address from the first transaction and the second memory address from the second transaction to the controller upon completion of the respective transactions.

US Patent:

20150082085, Mar 19, 2015

Filed:

Jul 11, 2014

Appl. No.:

14/329720

Inventors:

- San Jose CA, US
Poongovan Ponnavaikko - Santa Clara CA, US
Babu Neelam - Santa Clara CA, US

International Classification:

G06F 11/14
G06F 9/46

US Classification:

714 15

Abstract:

Techniques are disclosed for generating a multi-transactional system using transactional memory techniques. According to certain embodiments, a device may include a memory, one or more processing entities, and a transactional memory system for maintaining a plurality of transactional memory (TM) logs in a first portion of the memory. Each TM log may be associated with one transaction from a plurality of transactions sequentially executed by the one or more processing entities and each transaction comprises a plurality of operations. Furthermore, each TM log associated with each transaction comprises information associated with changes to a second portion of the memory caused by execution of operations from the transaction using the one or more processing entities. The TM logs for completed transactions may be used for error detection and recovery and maintaining high availability of the device.

US Patent:

20150074219, Mar 12, 2015

Filed:

Apr 30, 2014

Appl. No.:

14/266517

Inventors:

- San Jose CA, US
Poongovan Ponnavaikko - Santa Clara CA, US
Babu Neelam - Santa Clara CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

G06F 15/167
H04L 29/08

US Classification:

709213

Abstract:

Techniques for facilitating high availability in a device (e.g., a network device) comprising redundant processing entities (e.g., one or more processors, one or more cores, etc.) and a transactional memory system. The transactional memory system comprises a memory that is shareable between the redundant processing entities and ensures consistency of information stored in the memory at the atomicity of a transaction. A first processing entity may operate in a first mode (e.g., active mode) while a second processing entity operates in a second mode (e.g., standby mode). Operational state information used by the active processing entity for performing a set of functions in the first mode may be stored in the shared memory. Upon a switchover, the second processing entity may start to operate in the first mode and commence performing the set of functions using the operational state information stored by the transactional memory system.

US Patent:

20140089425, Mar 27, 2014

Filed:

Mar 15, 2013

Appl. No.:

13/840540

Inventors:

- San Jose CA, US
Poongovan Ponnavaikko - Santa Clara CA, US
Dan N. Retter - Cupertino CA, US
Mayur Mahajan - San Francisco CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

H04L 12/58

US Classification:

709206

Abstract:

Certain embodiments enable application message delivery to be automatically guaranteed for all failover scenarios through use of a novel infrastructure layer that supports high availability (HA) messaging. The High Availability Application Messaging Layer (HAML) can guarantee delivery of application messages whether a failover occurs at one or both of the source and the intended destination of the message. The HAML may transmit messages to one intended destination, as unicast messaging, or to multiple intended destinations, as multicast messaging. In some embodiments, the HAML may be HA aware, which refers to the awareness of the HAML of the redundancy for all processing entities within a network device to ensure hitless failover at the network device. By moving support for HA messaging from individual applications to the HAML, as a common infrastructure layer across the processing entities, the individual applications do not need to implement additional software to explicitly support HA messaging.

US Patent:

20140089484, Mar 27, 2014

Filed:

Mar 14, 2013

Appl. No.:

13/827641

Inventors:

- San Jose CA, US
Dan N. Retter - Cupertino CA, US
Mayur Mahajan - San Francisco CA, US
Poongovan Ponnavaikko - Santa Clara CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

H04L 12/24

US Classification:

709223

Abstract:

Certain embodiments of the present invention provide techniques that enable messages to be sent to a processing entity within a computing device without knowing the network address of the processing entity. In certain embodiments, instead of using the network address of the processing entity, a message can be communicated to the processing entity using information indicative of a role or state or function performed by the processing entity.