Narasimha B Bhat

US Patent:

55967434, Jan 21, 1997

Filed:

Jan 6, 1995

Appl. No.:

8/369291

Inventors:

Narasimha B. Bhat - Berkeley CA
Kamal Chaudhary - Berkeley CA

Assignee:

Regents of the University of California - Oakland CA

International Classification:

G06F 1900

US Classification:

395500

Abstract:

The architecture, operation and design of a novel Field Programmable Logic Device is described. The device implements a circuit by using a dynamic logic core that executes staged logic corresponding to the logic levels of the implemented circuit. Logic inputs to the dynamic logic core are obtained from a dynamic interconnection array. Appropriate logic inputs for a given logic level are dynamically selected and routed by the dynamic interconnection array. When necessary, the dynamic interconnection array buffers signals which are required at subsequent logic levels. The dynamic interconnection array selects logic inputs for a given logic level from circuit input signals, buffered signals and dynamic logic core output signals.