Akshath Shankar Bhat

Akshath Bhat Los Angeles, CA

view source

Work:

Wipro Technologies, VLSI Division
Bangalore, Karnataka
Jul 2011 to Jul 2013
ASIC Physical Design Engineer Indian Institute of Science
Bangalore, Karnataka
Jan 2011 to May 2011
Project Intern

Education:

Visvesvaraya Technological University
Belgaum, Karnataka
2007 to 2011
Bachelor of Engineering in Electronics and Communication Engineering University of Southern California
Los Angeles, CA
2013
Master's in Electrical Engineering

Skills:

TECHNICAL SKILLS EDA tools hands-on Experience: Synopsys IC Compiler, Synopsys Design Compiler, Synopsys Prime-Time STA suites, Mentor Graphics Calibre, Cadence Virtuoso, Atrenta Spy-Glass, Xilinx & Altera FPGA suites Handling Net-list to GDS-II, ASIC PnR flow for multiple blocks of multi-million digital gates in the cutting edge technology nodes, Timing Closure in multi-corner multi-mode, Physical Verification & Sign-off Floorplanning, Power/IO Planning and Power Estimations, Placement and optimizations, Clock Tree Synthesis, Routing and optimizations at block-level, Static Timing Analysis (STA) and Physical Verification: Design Rule Checks (DRC), Layout Versus Schematic (LVS) fixes using EDA tools Knowledge of Verilog/RTL coding, Unix shell, TCL & PERL scripting