Min Min Dai from 145 Elmwood Ave, Allendale, NJ 07401, age 46

Min Dai

License #:

28474 - Active

Issued Date:

Aug 6, 2010

Renew Date:

Dec 1, 2015

Expiration Date:

Nov 30, 2017

Type:

Certified Public Accountant

Min Dai

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Min Dai

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Senior Account Manager At New Alliance Consulting

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Location:

Greater New York City Area

Industry:

Public Relations and Communications

Min Dai Brooklyn, NY

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Work:

New York University Polytechnic School of Engineering, Brooklyn College

2011 to 2000
Research on hybrid materials of proteins and metal nanoparticles for drug carrying and delivery New York University Polytechnic School of Engineering
New York, NY
2011 to 2013
Research on internalization of artificial proteins for cancerous cells targeting New York University Polytechnic School of Engineering
New York, NY
2011 to 2012
Research on tri-block protein polymers for understanding of recombinant proteins New York University Polytechnic School of Engineering
New York, NY
2008 to 2011
Research on stimulus-responsive protein block polymer library for application in targeting cancerous cells Histogenetics
Ossining, NY
Jun 2008 to Aug 2008
Summer Internship Kyushu University
Fukuoka, Japan
2005 to 2006
Research on Conductivity of Poly (o-anthranilic acid) for Application in Fuel Cell

Education:

Polytechnic Institute of New York University
Brooklyn, NY
2007 to 2014
PhD in Chemistry Kyushu University
2002 to 2006
BS in Chemistry University of Science and Technology of China
Hefei, China
1997 to 1999
Business Administration

Skills:

Primary Research, Secondary Research; Word, Excel, PowerPoint, Keynote, Pages, Numbers, CDSSTR, ImageJ, FPCL, HPCL, UPLC, LC-MSUV-Vis, IR, TEM, NMR, MALDI-TOF MS, DSC, SDS-PAGE, ELISA, Biomek NXP, French Press, circular dichroism, fluorescent labeling, fluorescence measurement, cell culture, protein expression, protein purification, BCA assay, DNA miniprep, DNA transformation

US-China Relations in the Obama Administration: Facing Shared Challenges

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"US-China Relations in the OBAMA Administration: Facing Shared Challenges" presents a 21st century agenda and new grand strategy aligning China and America’s economic and national security in a new international system combining their and other peaceful nations’ military, economic and moral authorit...

Author
John Milligan-Whyte, Dai Min

Binding
Paperback

Pages
538

Publisher
New School Press Limited

ISBN #
0982280378

EAN Code
9780982280379

ISBN #
10

Integration of Green and Renewable Energy in Electric Power Systems

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A practical, application-oriented text that presents analytical results for the better modeling and control of power converters in the integration of green energy in electric power systems The combined technology of power semiconductor switching devices, pulse width modulation algorithms, and contro...

Author
Ali Keyhani, Mohammad N. Marwali, Min Dai

Binding
Hardcover

Pages
328

Publisher
Wiley

ISBN #
047018776X

EAN Code
9780470187760

ISBN #
7

Lonely Planet Shanghai (Travel Guide)

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Lonely Planet: The world's leading travel guide publisher Lonely Planet Shanghai is your passport to the most relevant, up-to-date advice on what to see and skip, and what hidden discoveries await you. Enjoy the Bund's spectacle of heritage architecture, wander the Yuyuan traditional Chinese gardens...

Author
Lonely Planet, Damian Harper, Min Dai

Binding
Paperback

Pages
320

Publisher
Lonely Planet

ISBN #
1743215711

EAN Code
9781743215715

ISBN #
4

Lonely Planet China (Travel Guide)

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Lonely Planet: The world's leading travel guide publisher Lonely Planet China is your passport to all the most relevant and up-to-date advice on what to see, what to skip, and what hidden discoveries await you. Get lost in the dynastic grandeur of Beijing's Forbidden City, hike along the Great Wall,...

Author
Lonely Planet, Damian Harper, Piera Chen, Min Dai, David Eimer, Tienlon Ho, Robert Kelly, Shawn Low, Emily Matchar, Daniel McCrohan

Binding
Paperback

Pages
1056

Publisher
Lonely Planet

ISBN #
1743214014

EAN Code
9781743214015

ISBN #
3

A White Paper For The Presidents of America And China

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The White Paper For the Presidents of America and China summarizes the seven books which present in detail the New School's conceptual framework, grand strategy, and agenda that are required to solve America and China's urgent economic crises and align their 21st century economic and national securi...

Author
John Milligan-Whyte

Binding
Paperback

Pages
184

Publisher
New School Press Ltd

ISBN #
0982280327

EAN Code
9780982280324

ISBN #
9

New China Business Strategies: Chinese and American Companies As Global Partners

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That is why How The West Can Profit From China s Economic Power is such an important and compelling work that will become a must-read book for corporate executives concerned about their business in China. A Western company without a carefully laid out China Strategy will find it increasingly diffic...

Author
John Milligan-whyte, Mannie Manhong Liu, Howard H. Jiang, Dai Min

Binding
Hardcover

Pages
351

Publisher
Specialist Press International

ISBN #
1561718203

EAN Code
9781561718207

ISBN #
6

China & America's Emerging Partnership: A Realistic New Perspective

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This book is about the evolving competitive relationships between the American and Chinese governments. It presents an urgently needed new perspective that recognises and responds to the reality that China's political, social, economic and legal systems, as well as business culture cannot and will n...

Author
John Milligan-whyte, Dai Min

Binding
Hardcover

Pages
506

Publisher
Specialist Press International

ISBN #
1561718718

EAN Code
9781561718719

ISBN #
5

Lonely Planet China (Country Travel Guide)

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Nobody knows China like Lonely Planet. Whether you want to sip cocktails in Shanghai, trek Tibet's holy Mt Kailash or contemplate history at Xu'an's Army of Terracotta Warriors, our 11th edition will guide you through the best of this jaw-dropping destination - and reveal more of it than any other g...

Author
Damian Harper, Chung Wah Chow, Min Dai, David Eimer, Carolyn Heller, Thomas Huhti, Robert Kelly, Daniel McCrohan, Christopher Pitts, Andrew Stone

Binding
Paperback

Pages
1036

Publisher
Lonely Planet

ISBN #
1741048664

EAN Code
9781741048667

ISBN #
2

Us Patents

Fabrication Of Silicon Oxide And Oxynitride Having Sub-Nanometer Thickness
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US Patent:

8492290, Jul 23, 2013
Filed:

Jun 21, 2011
Appl. No.:

13/164891
Inventors:

Michael P. Chudzik - Danbury CT, US
Min Dai - Mahwah NJ, US
Shahab Siddiqui - White Plains NY, US
Jinping Liu - Hopewell Junction NY, US
Assignee:

International Business Machines Corporation - Armonk NY
Globalfoundries Inc. - Grand Cayman
International Classification:

H01L 21/31
US Classification:

438765, 438767, 438769, 438770, 438786, 438787
Abstract:

A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000 C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000 C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0. 5 Å to 10 Å.

Method For Forming N-Shaped Bottom Stress Liner
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US Patent:

8557668, Oct 15, 2013
Filed:

Jan 12, 2012
Appl. No.:

13/348771
Inventors:

Xiaodong Yang - Hopewell Junction NY, US
Yanxiang Liu - Wappingers Falls NY, US
Vara Govindeswara Reddy Vakada - Beacon NY, US
Jinping Liu - Hopewell Junction NY, US
Min Dai - Mahwah NJ, US
Assignee:

GLOBALFOUNDRIES SINGAPORE Pte. Ltd. - Singapore
International Classification:

H01L 21/336
US Classification:

438296, 257E21561
Abstract:

Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.

Semiconductor Device Devoid Of An Interfacial Layer And Methods Of Manufacture
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US Patent:

20120280370, Nov 8, 2012
Filed:

May 2, 2011
Appl. No.:

13/098840
Inventors:

Michael P. CHUDZIK - Danbury CT, US
Min DAI - Mahwah NJ, US
Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:

H01L 29/06
H01L 21/31
US Classification:

257632, 438785, 257E2124, 257E2902
Abstract:

A method of forming a dielectric stack devoid of an interfacial layer includes subjecting an exposed interfacial layer provided on a semiconductor material to a low pressure thermal anneal process for a predetermined time period at a temperature of about 900 C. to about 1000 C. with an inert gas purge. A semiconductor structure is also disclosed, with a dielectric stack devoid of an interfacial layer.

Transistor With Reduced Parasitic Capacitance
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US Patent:

20130049142, Feb 28, 2013
Filed:

Aug 26, 2011
Appl. No.:

13/218988
Inventors:

Yanxiang Liu - Wappingers Falls NY, US
Jinping Liu - Hopewell Junction NY, US
Min Dai - Mahwah NJ, US
Xiaodong Yang - Hopewell Junction NY, US
Assignee:

International Business Machines Corporation - Armonk NY
GLOBALFOUNDRIES Singapore Pte. Ltd. - Singapore
International Classification:

H01L 29/78
H01L 21/336
US Classification:

257412, 438591, 257E29255, 257E21409
Abstract:

Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiOor low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiOor low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiOor low-k material, and forming a replacement metal gate in the remaining recess.

Method For Forming N-Type And P-Type Metal-Oxide-Semiconductor Gates Separately
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US Patent:

20130082332, Apr 4, 2013
Filed:

Sep 30, 2011
Appl. No.:

13/249643
Inventors:

Jinping Liu - Hopewell Junction NY, US
Min Dai - Mahwah NJ, US
Ju Youn Kim - Fishkill NY, US
Michael P. Chudzik - Ridgefield CT, US
Jedon Kim - Fishkill NY, US
Sungkee Han - Gyeonggi-do, KR
Assignee:

Samsung Electronics Co., Ltd. - Suwon-si
International Business Machines Corporation - Armonk NY
International Classification:

H01L 27/092
H01L 21/28
US Classification:

257369, 438592, 257E27062, 257E2119
Abstract:

Semiconductor devices with replacement gate electrodes are formed with different materials in the work function layers. Embodiments include forming first and second removable gates on a substrate, forming first and second pairs of spacers on opposite sides of the first and second removable gates, respectively, forming a hardmask layer over the second removable gate, removing the first removable gate, forming a first cavity between the first pair of spacers, forming a first work function material in the first cavity, removing the hardmask layer and the second removable gate, forming a second cavity between the second pair of spacers, and forming a second work function material, different from the first work function material, in the second cavity.

Germanium Oxide Free Atomic Layer Deposition Of Silicon Oxide And High-K Gate Dielectric On Germanium Containing Channel For Cmos Devices
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US Patent:

20130126986, May 23, 2013
Filed:

Nov 18, 2011
Appl. No.:

13/300146
Inventors:

MaryJane Brodsky - Salt Point NY, US
Murshed M. Chowdhury - Newburgh NY, US
Michael P. Chudzik - Danbury CT, US
Min Dai - Mahwah NJ, US
Siddarth A. Krishnan - Peekskill NY, US
Shreesh Narasimha - Beacon NY, US
Shahab Siddiqui - White Plains NY, US
Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:

H01L 29/772
H01L 21/336
US Classification:

257411, 438285, 438287, 257E21409, 257E29242
Abstract:

A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Semiconductor Device Including Graded Gate Stack, Related Method And Design Structure
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US Patent:

20130277765, Oct 24, 2013
Filed:

Apr 23, 2012
Appl. No.:

13/453131
Inventors:

Michael P. Chudzik - Danbury CT, US
Min Dai - Mahwah NJ, US
Jinping Liu - Hopewell Junction NY, US
Keith Kwong Hon Wong - Wappingers Falls NY, US
Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:

H01L 29/772
H01L 21/283
US Classification:

257411, 438585, 257E29242, 257E2119
Abstract:

A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Method Of Manufacturing Scaled Equivalent Oxide Thickness Gate Stacks In Semiconductor Devices And Related Design Structure
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US Patent:

20130330843, Dec 12, 2013
Filed:

Jun 7, 2012
Appl. No.:

13/490740
Inventors:

Michael P. Chudzik - Ridgefield CT, US
Min Dai - Mahwah NJ, US
Jinping Liu - Hopewell Junction NY, US
Paul A. Ronsheim - Barneveld WI, US
Shahab Siddiqui - White Plains NY, US
Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:

H01L 21/66
G06F 17/50
US Classification:

438 5, 716110, 257E2153
Abstract:

A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.

Min Min Dai

Min Dai Phones & Addresses

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Min Dai

Resumes

Min Dai

Min Dai

Senior Account Manager At New Alliance Consulting

Min Dai Brooklyn, NY

Amazon

US-China Relations in the Obama Administration: Facing Shared Challenges

Integration of Green and Renewable Energy in Electric Power Systems

Lonely Planet Shanghai (Travel Guide)

Lonely Planet China (Travel Guide)

A White Paper For The Presidents of America And China

New China Business Strategies: Chinese and American Companies As Global Partners

China & America's Emerging Partnership: A Realistic New Perspective

Lonely Planet China (Country Travel Guide)

Us Patents

Fabrication Of Silicon Oxide And Oxynitride Having Sub-Nanometer Thickness

Method For Forming N-Shaped Bottom Stress Liner

Semiconductor Device Devoid Of An Interfacial Layer And Methods Of Manufacture

Transistor With Reduced Parasitic Capacitance

Method For Forming N-Type And P-Type Metal-Oxide-Semiconductor Gates Separately

Germanium Oxide Free Atomic Layer Deposition Of Silicon Oxide And High-K Gate Dielectric On Germanium Containing Channel For Cmos Devices

Semiconductor Device Including Graded Gate Stack, Related Method And Design Structure

Method Of Manufacturing Scaled Equivalent Oxide Thickness Gate Stacks In Semiconductor Devices And Related Design Structure

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