Luverne R Peterson

US Patent:

6348814, Feb 19, 2002

Filed:

Feb 14, 2000

Appl. No.:

08/799953

Inventors:

LuVerne Peterson - San Diego CA

Assignee:

Cadenca Design Systems, Inc. - San Jose CA

International Classification:

H03K 1902

US Classification:

326 58, 326 27

Abstract:

A buffer circuit and method provide substantially constant output signal edges to facilitate service as a bus driver with enhanced timing flexibility. The buffer circuit includes a NOR gate and a NAND gate for driving output pulldown and pullup transistors. The initiation of current flows through the NOR and NAND gates is controlled by an environmentally adaptive reference circuit. First and second transistors are provided respectively between the NAND gate and the pullup transistor, and between the NOR gate and the pulldown transistor, to produce enhanced sourcing and sinking currents. The enhanced sinking and sourcing currents are timely terminated by switching of the pulldown and pullup transistors to save energy.

US Patent:

6381162, Apr 30, 2002

Filed:

Mar 19, 2001

Appl. No.:

09/811809

Inventors:

Luverne Peterson - San Diego CA

Assignee:

Tality, L.P. - San Jose CA

International Classification:

G11C 1501

US Classification:

365 49, 36518907, 36518911

Abstract:

A content addressable memory system has an array of CAM cells. Each row of the array has a match line coupled to a match line pull device. The match line pull devices of each cell are also coupled to a row return line that may be shared with an adjacent row. Each row return line is coupled through a resistive device to a rail. The CAM cells also have a data memory element and comparison logic for comparing query data against the data memory element and controlling the match line pull devices.

US Patent:

6385070, May 7, 2002

Filed:

Mar 13, 2001

Appl. No.:

09/805388

Inventors:

LuVerne Peterson - San Diego CA

Assignee:

Tality, L.P. - San Jose CA

International Classification:

G11C 1500

US Classification:

365 49, 365204

Abstract:

A content addressable memory system has rows and columns of CAM cells. Each CAM cell has a data memory, and comparison circuitry for comparing the data bit of the memory element with a compare data, and for driving a signal onto a match line when the data bit is not equal to the compare data. The comparison circuitry has a mismatch node with a pre-discharge device, and drives a match line drive device coupled to the match line. The mismatch node also couples to a first comparison device having source an output of the data memory and gate coupled to the compare data, and a second comparison device having source a second output of the data memory and gate coupled to compare data. Disclosed is a ternary implementation of the CAM cell also having a mask bit. Also disclosed is CAM timing such that the CAM cells operate without crowbar current.

US Patent:

6400592, Jun 4, 2002

Filed:

Sep 9, 2000

Appl. No.:

09/658544

Inventors:

LuVerne R. Peterson - San Diego CA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G11C 1500

US Classification:

365 49, 36518907, 365 94

Abstract:

A CAM cell design methodology and a method of pre-charge and comparison timing is disclosed. A CAM cell utilizing this design methodology includes a P-channel transistor configured to communicate a comparison result to a match line using the Miller effect. In one embodiment, the CAM cell further includes a positive comparison bit line, a negative comparison bit line, a first dual-ended CAM memory core cell configured to store data, a second dual-ended CAM memory core cell configured to store masking data, comparison circuitry, and a second P-channel transistor configured to communicate a masked state to the match line.

US Patent:

7271751, Sep 18, 2007

Filed:

Feb 8, 2006

Appl. No.:

11/350227

Inventors:

LuVerne Peterson - San Diego CA, US
Jonathan A. Levi - Fallbrook CA, US
Paul Abelovski - Escondido CA, US
Roger Mar - San Diego CA, US

Assignee:

Toshiba America Electronic Components, Inc. - San Diego CA

International Classification:

H03M 1/10

US Classification:

341120, 324763

Abstract:

A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.

US Patent:

7429882, Sep 30, 2008

Filed:

Jun 8, 2006

Appl. No.:

11/449325

Inventors:

Luverne R. Peterson - San Diego CA, US

Assignee:

Toshiba America Electronic Components, Inc.

International Classification:

H03K 3/00

US Classification:

327108, 330260

Abstract:

An inverting input buffer that uses the best features of an AC input buffer (low delay, high speed, high input voltage swing range) and a DC input buffer (stability, reliability, ‘automatic’ high and low data setup, input VIL and VIH “Voltage Input Low” and “Voltage Input High” margins). The delay though the buffer with a nominal load is very small. Optionally, a voltage tolerant input circuit is coupled to the DC input, which enables the DC input buffer to tolerate higher voltage swings, thus allowing a single buffer to switch both high (e. g. 2. 5 volts-5 volts in a 1. 2 volt system) and low input voltages (e. g. below 2. 5 volts in a 1. 2 volt system).

US Patent:

7893731, Feb 22, 2011

Filed:

Nov 19, 2008

Appl. No.:

12/273742

Inventors:

Luverne R. Peterson - San Diego CA, US

Assignee:

Toshiba America Electronic Components, Inc. - Irvine CA

International Classification:

H03B 1/00
H03K 3/00

US Classification:

327108, 327109, 327110, 327111, 327112, 330260

Abstract:

A non-inverting AC/DC input buffer combines the desirable characteristics of an alternating current (AC) input buffer including low delay, high speed, and high input voltage swing range with the desirable characteristics of a direct current (DC) input buffer including stability, reliability, and ‘automatic’ high and low data setup. The AC/DC buffer includes logic to help prevent the DC input buffer from interfering with the AC input buffer until the DC input buffer has completed its operations on a transitioning input. The DC buffer is configured to enable the AC buffer to process low input voltage swings such as, for example, voltage swings less than the difference in power supply voltages.

US Patent:

8262286, Sep 11, 2012

Filed:

Nov 18, 2008

Appl. No.:

12/273031

Inventors:

Luverne R. Peterson - San Diego CA, US
James R. Welch - Corcoran MN, US

Assignee:

Toshiba America Electronic Components, Inc. - Irvine CA

International Classification:

G01K 7/00

US Classification:

374170, 374171, 327512

Abstract:

A temperature sensor generates a digital output signal representative of the absolute temperature of the sensor. The sensor includes a first circuit configured to generate a complementary to absolute temperature (CTAT) voltage signal and a second circuit configured to generate a proportional to absolute temperature (PTAT) current signal. A comparator receives the CTAT and PTAT signals and generates a comparison signal based on a comparison between the signals. A converter circuit receives the comparison signal and generates a digital output signal based on the comparison signal. The digital output signal is representative of the temperature of the sensor.