Liang H Yin from 3591 Quail Lakes Dr, Stockton, CA 95207, age 72, Phone: 209 956-4655

Us Patents

Hardware-Independent Detection Of San Logical Volumes
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US Patent:

7975136, Jul 5, 2011
Filed:

Mar 28, 2007
Appl. No.:

11/692658
Inventors:

Liang Yin - San Jose CA, US
Assignee:

Symantec Corporation - Mountain View CA
International Classification:

G06F 15/177
US Classification:

713 2, 713100
Abstract:

A system and method for determining a designated boot volume of a computer system coupled to a SAN is disclosed. The computer system is configured to boot from a logical volume on the SAN using a corresponding bus interface. One or more logical volumes within the SAN are identified and have code written to them. The code is executable to determine whether or not the computer system is configured to boot from that logical volume and to determine configuration information stored on the identified logical volumes.

Allocation Of Tracker Resources In A Computing System
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US Patent:

8117320, Feb 14, 2012
Filed:

Jun 30, 2006
Appl. No.:

11/479377
Inventors:

Liang Yin - San Jose CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 15/16
US Classification:

709228, 709202, 709227, 709251, 370400, 370403
Abstract:

A number of caching agents are interconnected by a ring. A number of trackers of a home agent are pre-allocated to each of the number of caching agents. A tracker provides a permit for a caching agent to issue a request to the home agent. In case a caching agent needs to issue more requests to the home agent, the caching agent may borrow a tracker from another caching agent by sending a message via the ring to other caching agents. A caching agent receiving the borrowing message may either respond the borrowing message by lending a tracker pre-allocated to the corresponding caching agent, or deny the borrowing request by forwarding the borrowing message to another caching agent.

Unidirectional Sweep Training For An Interconnect
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US Patent:

8121239, Feb 21, 2012
Filed:

Feb 11, 2008
Appl. No.:

12/069460
Inventors:

Liang Yin - San Jose CA, US
Harry Muljono - Union City CA, US
Sunil Kumar - Santa Clara CA, US
Alex Kuperman - Campbell CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H04L 7/00
US Classification:

375355
Abstract:

In one embodiment, the present invention includes a receiver having a delay lock loop (DLL) to receive a clock signal and to generate a plurality of clock phases therefrom, and an offset controller including a first register set for a first phase interpolator and a second register set for a second phase interpolator. At initiation of a track pre-tune process, both phase interpolators are controlled to generate sampling signals at a common clock phase. Other embodiments are described and claimed.

Data Ordering In A Multi-Node System
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US Patent:

20090006712, Jan 1, 2009
Filed:

Jun 29, 2007
Appl. No.:

11/772062
Inventors:

FATMA EHSAN - Friends Colony, IN
Binata Bhattacharyya - Brookefield, IN
Namratha Jaisimha - Bangalore, IN
Liang Yin - San Jose CA, US
International Classification:

G06F 12/00
US Classification:

711 1
Abstract:

Methods and apparatuses for data ordering in a multi-node system that supports non-snoop memory transactions.

Avoiding Deadlocks In A Multiprocessor System
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US Patent:

7600080, Oct 6, 2009
Filed:

Sep 22, 2006
Appl. No.:

11/525585
Inventors:

Binata Bhattacharyya - Bangalore, IN
Chandra P. Joshi - Bangalore, IN
Chung-Chi Wang - Sunnyvale CA, US
Liang Yin - San Jose CA, US
Vivek Garg - Folsom CA, US
Phanindra K. Mannava - Folsom CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/00
US Classification:

711143, 711118, 711119, 711128, 711135, 711141, 711147, 711148
Abstract:

In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a memory, directing the first memory request to a writeback queue of the home agent if the first memory request is a writeback request and otherwise directing the first memory request to a second queue of the home agent. In this way, circular dependencies may be avoided. Other embodiments are described and claimed.

Fine Grain Level Memory Power Consumption Control Mechanism
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US Patent:

20220276955, Sep 1, 2022
Filed:

May 13, 2022
Appl. No.:

17/744615
Inventors:

- Suwon-si, KR
Liang YIN - San Jose CA, US
International Classification:

G06F 12/00
G11C 5/14
G06F 1/3234
G06F 1/3225
Abstract:

According to one general aspect, an apparatus may include a memory module. The memory module may include a plurality of memory banks configured to store data. The memory module may include a plurality of memory bank power down controllers, each configured to place one or more respective memory bank(s) in a power down mode. The memory module may include a memory module command interface configured to receive a handshake command from a memory controller, wherein the handshake command comprises a command to remove an indicated memory bank from power down mode.

Error Containment For Enabling Local Checkpoint And Recovery
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US Patent:

20230011863, Jan 12, 2023
Filed:

Jul 12, 2021
Appl. No.:

17/373678
Inventors:

- Santa Clara CA, US
SAURABH HUKERIKAR - Santa Clara CA, US
PAUL RACUNAS - Landaff NH, US
NIRMAL RAJ SAXENA - LOS ALTOS HILLS CA, US
DAVID CHARLES PATRICK - MADISON AL, US
YIYANG FENG - San Jose CA, US
ABHIJEET GHADGE - San Jose CA, US
STEVEN JAMES HEINRICH - Madison AL, US
ADAM HENDRICKSON - San Jose CA, US
GENTARO HIROTA - Sunnyvale CA, US
PRAVEEN JOGINIPALLY - San Jose CA, US
VAISHALI KULKARNI - Sunnyvale CA, US
PETER C. MILLS - San Jose CA, US
SANDEEP NAVADA - San Jose CA, US
MANAN PATEL - San Jose CA, US
LIANG YIN - San Jose CA, US
International Classification:

G06F 11/10
G06F 11/07
G06F 11/14
G06F 12/1027
G06F 12/1018
Abstract:

Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

Computing System With Communication Mechanism
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US Patent:

20190272111, Sep 5, 2019
Filed:

May 16, 2019
Appl. No.:

16/414555
Inventors:

- Suwon-si, KR
Liang Yin - San Jose CA, US
Hongzhong Zheng - Sunnyvale CA, US
International Classification:

G06F 3/06
Abstract:

A computing system including: a host interface configured to parse a command packet from a command address medium; and a command block, coupled to the host interface, configured to: assemble a command from the command packet.