Jinsong Yin

US Patent:

6830998, Dec 14, 2004

Filed:

Jun 17, 2003

Appl. No.:

10/462667

Inventors:

James Pan - Fishkill NY
Paul Besser - Sunnyvale CA
Christy Mei-Chu Woo - Cupertino CA
Minh Van Ngo - Fremont CA
Jinsong Yin - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438592, 926229, 926299

Abstract:

Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.

US Patent:

6861350, Mar 1, 2005

Filed:

Jun 19, 2003

Appl. No.:

10/464508

Inventors:

Minh Van Ngo - Fremont CA, US
Christy Mei-Chu Woo - Cupertino CA, US
Jinsong Yin - Sunnyvale CA, US
James Pan - Fishkill NY, US
Paul R. Besser - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H10L021/4763
H10L021/44

US Classification:

438627, 438643, 438653

Abstract:

Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.

US Patent:

6893910, May 17, 2005

Filed:

Jun 17, 2003

Appl. No.:

10/462670

Inventors:

Christy Mei-Chu Woo - Cupertino CA, US
Paul R. Besser - Sunnyvale CA, US
Minh Van Ngo - Fremont CA, US
James N. Pan - Fishkill NY, US
Jinsong Yin - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/338
H01L021/336
H01L021/3205
H01L021/31

US Classification:

438183, 438287, 438591, 438785

Abstract:

A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed to create a TaOregion and a Ta region from the deposited oxide and Ta. This creates a low carbon-content TaOand a metallic Ta gate in a single process step.

US Patent:

6927162, Aug 9, 2005

Filed:

Feb 23, 2004

Appl. No.:

10/782874

Inventors:

Wen Yu - Fremont CA, US
Jinsong Yin - Sunnyvale CA, US
Connie Pin-Chin Wang - Menlo Park CA, US
Paul Besser - Sunnyvale CA, US
Keizaburo Yoshie - Cupertino CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/4763
H01L021/44

US Classification:

438637, 438644, 438648, 438649, 438675

Abstract:

A method of forming a contact in a semiconductor device deposits a refractory metal contact layer in a contact hole on a conductive region portion in a silicon substrate. The refractory metal contact layer is reacted with the silicide region prior to a plasma treatment of a contact barrier metal layer formed within the contact hole. This prevents portions of the refractory metal contact layer from being nitridated prior to conversion to silicide.

US Patent:

7033888, Apr 25, 2006

Filed:

Mar 23, 2004

Appl. No.:

10/806117

Inventors:

James N. Pan - Santa Clara CA, US
Paul R. Besser - Sunnyvale CA, US
Christy Woo - Cupertino CA, US
Minh Van Ngo - Fremont CA, US
Jinsong Yin - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/336

US Classification:

438257, 438299, 438303

Abstract:

A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

US Patent:

7060571, Jun 13, 2006

Filed:

Feb 13, 2004

Appl. No.:

10/777138

Inventors:

Minh Van Ngo - Fremont CA, US
Christy Woo - Cupertino CA, US
James Pan - Fishkill NY, US
Paul R. Besser - Sunnyvale CA, US
Jinsong Yin - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/336

US Classification:

438287, 438785

Abstract:

Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing a thin tantalum film, as by PVD at a thickness of 25 Å to 60 Å lining the opening, and then conducting thermal oxidation, as at a temperature of 100 C. to 500 C. , in flowing oxygen or ozone to form a high-k tantalum oxide gate dielectric layer, or in oxygen and NO or ozone and NO ammonia to form a high-k tantalum oxynitride gate dielectric. Alternatively, oxidation can be conducted in an oxygen or ozone plasma to form the high-k tantalum oxide layer, or in a plasma containing NO and oxygen or ozone to form the high-k tantalum oxynitride gate dielectric layer.

US Patent:

7071086, Jul 4, 2006

Filed:

Apr 23, 2003

Appl. No.:

10/420721

Inventors:

Christy Woo - Cupertino CA, US
Paul Besser - Sunnyvale CA, US
Minh van Ngo - Fremont CA, US
James Pan - Santa Clara CA, US
Jinsong Yin - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale VA

International Classification:

H01L 21/3205

US Classification:

438592

Abstract:

A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.

US Patent:

7217660, May 15, 2007

Filed:

Apr 19, 2005

Appl. No.:

11/109964

Inventors:

Connie Pin-Chin Wang - Mountain View CA, US
Paul R. Besser - Sunnyvale CA, US
Jinsong Yin - Sunnyvale CA, US
Hieu T. Pham - Milpitas CA, US
Minh Van Ngo - Fremont CA, US

Assignee:

Spansion LLC - Sunnyvale CA
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/22

US Classification:

438685, 438700

Abstract:

A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.