Larry C Novak

US Patent:

39393356, Feb 17, 1976

Filed:

Nov 26, 1974

Appl. No.:

5/527510

Inventors:

George L. Brantingham - Richardson TX
Louis H. Phillips - Dallas TX
Larry T. Novak - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1502

US Classification:

235156

Abstract:

A greatly simplified calculator circuit implemented, for example, utilizing I. sup. 2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a universal condition latch which is so connected as to permit the state thereof to be determined by multiple sources while reducing the number of ROM instructions required and hence the size of the ROM to permit fabrication on the smaller chip. The condition latch state is determined, for example, by the logical OR of up to four flags after a test flag instruction, by the logical OR of up to four keyboard inputs after a test key instruction, by the carry output of the adder after any add instruction, or by the results of an adder compare after any compare instruction.

US Patent:

39566200, May 11, 1976

Filed:

Nov 26, 1974

Appl. No.:

5/527506

Inventors:

George L. Brantingham - Richardson TX
Larry T. Novak - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 750
G06F 1502

US Classification:

235156

Abstract:

A greatly simplified calculator circuit implemented, for example, utilizing I. sup. 2 L technology is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a dual adder which selectively functions as a multibit word adder and also as a plurality of single bit adders. This dual functioning adder cooperates with the calculator system in such a manner as to reduce the total amount of circuitry required to implement the calculator function thereby permitting fabrication on the smaller chip. The dual adder is utilized, for example, to perform bit operations for use in flagging and 2's complement addition for subtraction operations as well as normal multibit word addition.