Kwang Il Kim

Address:

2561 Flagstone Dr, San Jose, CA 95132

VIN:

JTHBE96SX70024385

Make:

LEXUS

Model:

GS 350

Year:

2007

US Patent:

6424190, Jul 23, 2002

Filed:

Sep 13, 2001

Appl. No.:

09/950572

Inventors:

Kwang Y. Kim - Irvine CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 700

US Classification:

327144, 327258, 327309

Abstract:

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

US Patent:

6493191, Dec 10, 2002

Filed:

Sep 15, 1995

Appl. No.:

08/528890

Inventors:

William C. Cain - San Jose CA
Richard D. Anderson - Sunnyvale CA
Michael A. Baldwinson - Cupertino CA
Keith R. Berding - San Jose CA
Michael E. Devillier - San Jose CA
Garrett A. Garrettson - Los Altos Hills CA
Randolph S. Gluck - San Jose CA
Harold J. Hamilton - Santa Clara CA
Robert D. Hempstead - Los Gatos CA
Darren T. Imai - Los Gatos CA
Kwang K. Kim - Saratoga CA
Dimitre A. Latev - San Jose CA
Alexander P. Payne - Ben Lomond CA
David D. Roberts - Santa Cruz CA

Assignee:

Censtor Corporation - Los Gatos CA

International Classification:

G11B 5187

US Classification:

3602462, 3602461

Abstract:

A transducer for a hard disk drive system has a planar magnetic core and a pair of poletips that project transversely from the core for sliding contact with the disk during reading and writing. The transducer is formed entirely of thin films in the shape of a low profile table having three legs that slide on the disk, the poletips being exposed at a bottom of one of the legs for high resolution communication with the disk, the throat height of the poletips affording sufficient tolerance to allow for wear. The legs elevate the transducer from the disk sufficiently to minimize lifting by a thin air layer that moves with the spinning disk which, in combination with the small size of the thin film head allows a low load and a flexible beam and gimbal to hold the transducer to the disk. The transducer includes a loop shaped core of magnetic material that ends at the poletips, the core extending further parallel than perpendicular to the disk surface and preferably being formed of a plurality of slightly spaced ribbons of magnetic material in order to increase high frequency permeance. A high magnetic saturation layer may be formed adjoining the gap in at least the trailing poletip, in order to avoid saturation at the poletips during writing.

US Patent:

6542383, Apr 1, 2003

Filed:

Oct 3, 2001

Appl. No.:

09/970189

Inventors:

Brian Tsuyuki - Roseville CA
Herbert J. Tanzer - Folsom CA
Kwang H. Kim - Santa Clara CA
Tanya Schneider - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H05K 900

US Classification:

361816, 361800, 361818, 361801, 361728, 361796, 361803

Abstract:

Systems for mounting electronic components are provided. An exemplary system includes a module that is configured to mount to a chassis at a first pitch. The module incorporates a housing, which is adapted to at least partially encase an electronic component, and spring fingers that are arranged at least partially about an exterior of the housing. The spring fingers are configured to deflect in response to a displacement force so that the module can be mounted to a chassis. The module can be mounted to a first chassis that accommodates a predetermined pitch of modules. In some embodiments, the module also can be mounted at a different pitch. Other systems also are provided.

US Patent:

6597216, Jul 22, 2003

Filed:

Jul 19, 2002

Appl. No.:

10/197843

Inventors:

Kwang Y. Kim - Irvine CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 700

US Classification:

327144, 327258, 327309

Abstract:

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

US Patent:

6791379, Sep 14, 2004

Filed:

Dec 7, 1999

Appl. No.:

09/456230

Inventors:

Myles Wakayama - Laguna Niguel CA
Stephen A. Jantzi - Laguna Beach CA
Kwang Young Kim - Irvine CA
Yee Ling Felix Cheung - Irvine CA
Ka Wai Tong - Aliso Viejo CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 706

US Classification:

327156

Abstract:

A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

US Patent:

6906564, Jun 14, 2005

Filed:

Jul 21, 2003

Appl. No.:

10/622708

Inventors:

Kwang Y. Kim - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L007/00

US Classification:

327144, 327258, 327309

Abstract:

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

US Patent:

6963245, Nov 8, 2005

Filed:

Sep 3, 2003

Appl. No.:

10/653348

Inventors:

Josephus A. E. P. van Engelen - Aliso Viejo CA, US
Kwang Young Kim - Irvine CA, US
Mark J. Chambers - Mission Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03F003/45

US Classification:

330259, 330253

Abstract:

A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.

US Patent:

6975557, Dec 13, 2005

Filed:

Apr 27, 2004

Appl. No.:

10/832262

Inventors:

Lionel J. D'Luna - Irvine CA, US
Mark Chambers - Mission Viejo CA, US
Thomas Hughes - Dana Point CA, US
Kwang Y. Kim - Irvine CA, US
Sathish K. Radhakrishnan - Karnataka, IN

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C008/00

US Classification:

365233, 365193, 365194

Abstract:

A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.