Bok S Kim

US Patent:

6355571, Mar 12, 2002

Filed:

Jul 30, 1999

Appl. No.:

09/365129

Inventors:

Judy H. Huang - Los Gatos CA
Christopher Dennis Bencher - Sunnyvale CA
Sudha Rathi - San Jose CA
Christopher S. Ngai - Burlingame CA
Bok Hoen Kim - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438706, 438573

Abstract:

A method and apparatus for reducing oxidation of an interface of a semiconductor device thereby improving adhesion of subsequently formed layers and/or devices is disclosed. The semiconductor device has at least a first layer and a second layer wherein the interface is disposed between said first and second layers. The method includes the steps of providing the first layer having a partially oxidized interface; introducing a hydrogen-containing plasma to the interface; reducing the oxidized interface and introducing second-layer-forming compounds to the hydrogen-containing plasma. A concomitant apparatus (i. e. , a semiconductor device interface) has a first insulating layer, one or more conductive devices disposed within the insulating layer, the insulating layer and conductive devices defining the interface, wherein the interface is treated with a continuous plasma treatment to remove oxidation and deposit a second layer thereupon. The insulating layer of the interface is selected from oxides and nitrides and is preferably a nitride.

US Patent:

6413321, Jul 2, 2002

Filed:

Dec 7, 2000

Appl. No.:

09/731601

Inventors:

Bok Hoen Kim - San Jose CA
Mario Dave Silvetti - Morgan Hill CA
Ameeta Madhava - San Francisco CA
Davood Khalili - Santa Clara CA
Martin Seamons - San Jose CA
Emanuele Cappello - Saratoga CA
Nam Le - San Jose CA
Lloyd Berken - Fremont CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1600

US Classification:

118725, 118719, 438680, 438758, 438765

Abstract:

Backside particle contamination of semiconductor wafers subjected to chemical vapor deposition is significantly reduced by optimizing various process parameters, alone or in combination. A high quality oxide seasoning layer is deposited to improve adhesion and trapping of contaminants remaining after a prior chamber cleaning step. Second, wafer pre-heating reduces thermal stress on the wafer during physical contact between the wafer and heater. Third, the duration of the gas stabilization flow of thermally reactive process gas species prior to CVD reaction is reduced, thereby preventing side products produced during this stabilization flow from affecting the wafer backside. Fourth, the wafer heater is redesigned to minimize physical contact between the heater surface and the wafer backside. Redesign of the wafer heater may include providing only a few, small projections from the top wafer surface, and also may include providing a continuous circumferential rim supporting the edge of the wafer to interfere with the flow of process gases to the wafer backside during processing.

US Patent:

6436303, Aug 20, 2002

Filed:

Jul 21, 1999

Appl. No.:

09/359148

Inventors:

Bok Heon Kim - San Jose CA
Nam Le - San Jose CA
Joseph V. DSouza - Sunnyvale CA
Ashish Shrotriya - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2100

US Classification:

216 67, 134 11, 134 12, 438710, 438727, 438731

Abstract:

A method and device for removing film from a substrate are provided that take advantage of a remote plasma source to etch away undesired portions of films, such as dielectric films formed on a substrate. To that end, the method includes forming a plasma remotely with respect to the process chamber, from which a flow is created that is directed toward the substrate. The substrate is of a type having opposed major surfaces with a peripheral surface extending therebetween. A film, such as a dielectric film, is disposed on one of the opposed major surfaces and on the peripheral surface. The opposed major surface having the film thereon is shielded from the flow of reactive radicals while the peripheral surface is left exposed. In this fashion, the flow is maintained for a sufficient amount of time to remove film present on the peripheral surface.

US Patent:

6700202, Mar 2, 2004

Filed:

Dec 7, 2001

Appl. No.:

10/013182

Inventors:

Judy H. Huang - Los Gatos CA
Christopher Dennis Bencher - Sunnyvale CA
Sudha Rathi - San Jose CA
Christopher S. Ngai - Burlingame CA
Bok Hoen Kim - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2348

US Classification:

257762, 438622

Abstract:

A method and apparatus for reducing oxidation of an interface of a semiconductor device thereby improving adhesion of subsequently formed layers and/or devices is disclosed. The semiconductor device has at least a first layer and a second layer wherein the interface is disposed between said first and second layers. The method includes the steps of providing the first layer having a partially oxidized interface; introducing a hydrogen-containing plasma to the interface; reducing the oxidized interface and introducing second-layer-forming compounds to the hydrogen-containing plasma. A concomitant apparatus (i. e. , a semiconductor device interface) has a first insulating layer, one or more conductive devices disposed within the insulating layer, the insulating layer and conductive devices defining the interface, wherein the interface is treated with a continuous plasma treatment to remove oxidation and deposit a second layer thereupon. The insulating layer of the interface is selected from oxides and nitrides and is preferably a nitride.

US Patent:

6843881, Jan 18, 2005

Filed:

Apr 2, 2002

Appl. No.:

10/115526

Inventors:

Bok Hoen Kim - San Jose CA, US
Nam Le - San Jose CA, US
Martin Seamons - San Jose CA, US
Ameeta Madhava - San Francisco CA, US
Michael P. Nault - Woodland Park CO, US
Thomas Nowak - Cupertino CA, US
Tsutomu Tanaka - Santa Clara CA, US
Moshe Sarfaty - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21306

US Classification:

15634525, 15634524, 15634529, 15634535, 15634551, 134 56 R

Abstract:

In a substrate processing apparatus, a substrate processing chamber has a substrate support to support a substrate, a gas delivery system to provide an energized cleaning gas to the chamber to clean process residues formed on surfaces in the chamber during processing of the substrate, and an exhaust to exhaust the cleaning gas. A detector monitors a chemiluminescent radiation emitted from about a surface during cleaning of the process residues by the energized cleaning gas and generates a signal in relation to the monitored chemiluminescent radiation. A controller receives the signal and evaluates the signal to determine an endpoint of the cleaning process.

US Patent:

6868856, Mar 22, 2005

Filed:

Jul 13, 2001

Appl. No.:

09/905515

Inventors:

Thomas Nowak - Cupertino CA, US
Ian Latchford - Sunnyvale CA, US
Tsutomu Tanaka - Santa Clara CA, US
Bok Heon Kim - San Jose CA, US
Ping Xu - Fremont CA, US
Jason Foster - Santa Clara CA, US
Heath B. DeShong - Livermore CA, US
Martin Seamons - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B08B006/00
H01L021/306

US Classification:

134 11, 134 1, 134 12, 134 13, 134 56 R, 134902, 216 67, 15634524, 15634535, 20419232, 20419235, 20419236

Abstract:

Methods and apparatus for cleaning semiconductor processing equipment. The apparatus include both local and remote gas dissociators coupled to a semiconductor processing chamber to be cleaned. The methods include introducing a precursor gas into the remote dissociator where the gas is dissociated and introducing a portion of the dissociated gas into the chamber. Another portion of the dissociated gas which re-associates before introduction into the chamber is also introduced into the chamber where it is again dissociated. The dissociated gas combines with contaminants in the chamber and is exhausted from the chamber along with the contaminants.

US Patent:

6927178, Aug 9, 2005

Filed:

Dec 10, 2003

Appl. No.:

10/732904

Inventors:

Bok Hoen Kim - San Jose CA, US
Sudha Rathi - San Jose CA, US
Sang H. Ahn - Foster City CA, US
Christopher D. Bencher - San Jose CA, US
Yuxiang May Wang - Palo alto CA, US
Hichem M'Saad - Santa clara CA, US
Mario D. Silvetti - Morgan Hill CA, US
Miguel Fung - Redwood City CA, US
Keebum Jung - Gilroy CA, US
Lei Zhu - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L021/31
H01L021/469

US Classification:

438778, 438790, 438952

Abstract:

Methods are provided for depositing a dielectric material. The dielectric material may be used for an anti-reflective coating or as a hardmask. In one aspect, a method is provided for processing a substrate including introducing a processing gas comprising a silane-based compound and an oxygen and carbon containing compound to the processing chamber and reacting the processing gas to deposit a nitrogen-free dielectric material on the substrate. The dielectric material comprises silicon and oxygen. In another aspect, the dielectric material forms one or both layers in a dual layer anti-reflective coating.

US Patent:

6946401, Sep 20, 2005

Filed:

Sep 4, 2003

Appl. No.:

10/655438

Inventors:

Judy H. Huang - Los Gatos CA, US
Christopher Dennis Bencher - Sunnyvale CA, US
Sudha Rathi - San Jose CA, US
Christopher S. Ngai - Burlingame CA, US
Bok Hoen Kim - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L021/302

US Classification:

438706, 438573

Abstract:

The present invention provides an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications.