Krishnaswamy V Nagaraj

US Patent:

6369726, Apr 9, 2002

Filed:

Sep 13, 2000

Appl. No.:

09/660816

Inventors:

Krishnaswamy Nagaraj - Somerville NJ
Shanthi Y. Pavan - Piscataway NJ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 100

US Classification:

341122, 341155

Abstract:

A fast acting polarity detector uses a âvery fastâ polarity detector in tandem with a âpreciseâ polarity detector to increase the maximum speed achievable from an A/D converter that employs a 1-bit folding front end. The fast polarity detector is a coarse polarity detector that immediately controls the 1-bit folder. The precise polarity detector operates more slowly, but more accurately. When the output of the precise polarity detector becomes available, it overrides the output of the fast polarity detector. This process does not limit the speed of the A/D conversion even though the precise polarity detector is slower to operate since the signal levels are small.

US Patent:

6404262, Jun 11, 2002

Filed:

Nov 17, 2000

Appl. No.:

09/715661

Inventors:

Krishnaswamy Nagaraj - Somerville NJ
T. R. Viswanathan - Addison TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 764

US Classification:

327336, 327 95, 327 94, 327554

Abstract:

An exemplary electronic circuit of the present include first and second buffers and , which are preferably unity gain buffers. A first switch (e. g. , a NMOS transistor or a CMOS transmission gate) is coupled between the output of the first buffer and the first terminal of a capacitor. The input of the second buffer is also coupled to the first terminal of the capacitor. A second switch is coupled between the second terminal of the capacitor and a first voltage node V and a third switch is coupled between the second terminal of the capacitor and a second voltage node V. This circuit can be used as an integrator in a number of applications.

US Patent:

6411246, Jun 25, 2002

Filed:

Dec 18, 2000

Appl. No.:

09/739188

Inventors:

Krishnaswamy Nagaraj - Somerville NJ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 134

US Classification:

341158, 341155, 341156, 341157, 341159, 341160

Abstract:

A folding circuit is provided for outputting a periodic function representative of an analog input signal. The circuit includes at least two preamplifiers and a third differential amplifier circuit coupled to the preamplifier circuits for providing a bias current such that the flow of current is regulated through one of the preamplifier circuits at any given time, thereby providing a periodic function representative of an analog input signal.

US Patent:

6414611, Jul 2, 2002

Filed:

Apr 7, 2000

Appl. No.:

09/545550

Inventors:

Krishnaswamy Nagaraj - Somerville NJ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 106

US Classification:

341118, 341122, 341 155

Abstract:

A method and circuit for improving the aperture distortion in parallel A/D converters by reducing the delay mismatch in the sample-and-hold portion of A/D converter circuit. The technique involves generating two complementary clocks, Q and {overscore (Q)}, from a single master clock and then gating these two clocks, in a random fashion, with the original master clock in order to significantly reduce the delay mismatch in the circuit. This approach involves the random selection of gated switches from dual banks each containing a plurality of parallel switches, thereby compensating for aperture error by converting any systematic aperture mismatch between the sampling clocks into random noise spread over the frequency band. High speed A/D converters incorporating the techniques of this invention will provide superior performance in digital audio, digital video, and many other digital applications.

US Patent:

6437724, Aug 20, 2002

Filed:

Sep 14, 2000

Appl. No.:

09/662274

Inventors:

Krishnaswamy Nagaraj - Somerville NJ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 136

US Classification:

341159, 341155

Abstract:

An electronic circuit for converting an analog differential signal into a corresponding digital signal includes 2 voltage comparators each having a first input terminal, a second input terminal and an output terminal. A first network of 2 resistive elements is provided to which a first analog signal of the differential signal is applied, the first network having a plurality of first network nodes each coupled to the first input terminal of a corresponding one of the comparators and wherein one of the first network nodes is a first middle node coupled to the first analog signal. A second network of 2 resistive elements is provided to which a second analog signal of the differential signal is applied, the second network having a plurality of second network nodes each coupled to the second input terminal of the corresponding one of the comparators and wherein one of the second network nodes is a second middle node coupled to the second analog signal. The disclosed circuit couples a differential input signal to the capacitor array without the need for capacitors. This simplifies implementation and saves power and area.

US Patent:

6441769, Aug 27, 2002

Filed:

Dec 22, 2000

Appl. No.:

09/745771

Inventors:

Krishnaswamy Nagaraj - Somerville NJ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 110

US Classification:

341161, 341120

Abstract:

An apparatus for correcting for the finite gain of an amplifier assembly in a pipelined analog to digital converter (ADC) is disclosed in which an input signal to an amplifier module of one stage of the pipelined ADC is sampled and provided to the input of an amplifier of a subsequent stage as a feed-forward error correction signal. The feed-forward correction signal is subtracted in the next stage from the output residue signal of the previous stage input to the second subsequent stage amplifier in order to remove part of the output signal from the first stage that includes the finite gain of the amplifier.

US Patent:

6522489, Feb 18, 2003

Filed:

Oct 25, 2000

Appl. No.:

09/696315

Inventors:

Krishnaswamy Nagaraj - Somerville NJ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 509

US Classification:

360 32, 360 46, 341156

Abstract:

An analog-to-digital converter includes first and second analog-to-digital converters and both of which receive an input signal. The first analog-to-digital converter is configured to be centered around a first signal level point while the second analog-to-digital converter is configured to be centered around a second signal level point. A decoder receives inputs from the two analog-to-digital converters and and selects between the first analog-to-digital converter output and the second analog-to-digital converter output.

US Patent:

7719299, May 18, 2010

Filed:

Apr 2, 2008

Appl. No.:

12/061409

Inventors:

Baher S. Haroun - Allen TX, US
Gaurav Chandra - Richardson TX, US
Vijaya Bhaskar Rentala - Plano TX, US
Venkatesh Srinivasan - Dallas TX, US
Hisashi Shichijo - Plano TX, US
Krishnaswamy Nagaraj - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/02
H01L 21/66

US Classification:

324763, 324765, 3241581

Abstract:

In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.