Kenneth D Holberger

US Patent:

56088655, Mar 4, 1997

Filed:

Mar 14, 1995

Appl. No.:

8/405178

Inventors:

Christopher W. Midgely - Framingham MA
Charles Holland - Northboro MA
Kenneth D. Holberger - Grafton MA

Assignee:

Network Integrity, Inc. - Marlborough MA

International Classification:

G06F 1100

US Classification:

395180

Abstract:

An Integrity Server computer for economically protecting the data of a computer network's servers, and providing hot standby access to up-to-date copies of the data of a failed server. As the servers' files are created or modified, they are copied to the Integrity Server. When one of the servers fails, the Integrity Server fills in for the failed server, transparently providing the file service of the failed server to network clients. The invention provides novel methods for managing the data stored on the Integrity Server, so that the standby files are stored on low-cost media such as tape, but are quickly copied to disk when a protected server fails. The invention also provides methods for re-establishing connections between clients and servers, and communicating packets between network nodes, to allow the Integrity Server to stand-in for a failed server without requiring reconfiguration of the network clients.

US Patent:

44096550, Oct 11, 1983

Filed:

Apr 25, 1980

Appl. No.:

6/143981

Inventors:

Steven Wallach - Framingham MA
Kenneth D. Holberger - North Grafton MA
David L. Keating - Natick MA
Steven M. Staudaher - Northboro MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 900
G06F 932
G06F 934

US Classification:

364200

Abstract:

A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses. The system uses hierarchical memory storage using in a particular embodiment eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The segment locations are designated by successive segment numbers having a descending order of protection with reference to data accesses thereto. A current address for data access includes a segment identification and a comparison is made with the segment identification of a preceding address to determine whether access can be made by the current address.

US Patent:

43863990, May 31, 1983

Filed:

Apr 25, 1980

Appl. No.:

6/143561

Inventors:

Edward Rasala - Westboro MA
Steven Wallach - Framingham MA
Carl J. Alsing - Hopkington MA
Kenneth D. Holberger - North Grafton MA
Charles J. Holland - Northboro MA
Thomas West - Boxboro MA
James M. Guyer - Marlboro MA
Richard W. Coyle - Dunstable MA
Michael L. Ziegler - Whitinsville MA
Michael B. Druke - Chelmsford MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 936

US Classification:

364200

Abstract:

A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.

US Patent:

47424494, May 3, 1988

Filed:

Oct 21, 1985

Appl. No.:

6/789355

Inventors:

David I. Epstein - Framingham MA
Kenneth D. Holberger - North Grafton MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 922

US Classification:

364200

Abstract:

A data processing system in which macroinstructions are decoded to provide a sequence of microinstructions comprising one or more microroutines. If a fault condition occurs, the currently executing microinstruction of a sequence thereof is interrupted, while the fault is being handled. When the fault has been resolved, execution of the interrupted microinstruction resumes. If the fault cannot be resolved the sequence of microinstructions is permanently aborted. The process of interrupting the sequence and resuming operation at the interrupted microinstruction is essentially invisible to the microprogram.

US Patent:

44032820, Sep 6, 1983

Filed:

Apr 29, 1980

Appl. No.:

6/144884

Inventors:

Kenneth D. Holberger - Marlboro MA
Joseph E. Samson - Framingham MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A data processing system having a central processor unit (CPU) and a memory and further including a high speed, or "burst multiplexer", channel for permitting direct access to the memory by an input/output (I/O) device without the need to use registers and control signals from the central processor unit. The high speed channel utilizes its own memory port separate from that of the CPU and includes internal paths for transferring addresses and data between an I/O device and the memory. The channel further includes a memory allocation unit (MAP) which can be loaded by transfer of memory allocation data via substantially the same common path as the I/O data transfer. Appropriate control logic is also included to control the data and address transfers and the MAP load and dump operations so that blocks of data words can be transferred sequentially and directly to or from the memory.