Kang R Choi

US Patent:

6404065, Jun 11, 2002

Filed:

Jul 31, 1998

Appl. No.:

09/134664

Inventors:

Kang Rim Choi - Cupertino CA

Assignee:

I-XYS Corporation - Santa Clara CA

International Classification:

H01L 2348

US Classification:

257782, 257787, 257678, 257693, 257690, 257719, 257706, 257708, 257701, 257675, 438133, 438122, 438123, 438124

Abstract:

A packaged power semiconductor device ( ) with voltage isolation between a metal backside ( ) and the terminals ( ) of the device. A direct-bonded copper (âDBCâ) substrate ( ) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die ( ) is soldered or otherwise mounted to a first metal layer ( ) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.

US Patent:

6534343, Mar 18, 2003

Filed:

May 8, 2001

Appl. No.:

09/851696

Inventors:

Kang Rim Choi - Cupertino CA

Assignee:

Ixys Corporation - Santa Clara CA

International Classification:

H01L 2148

US Classification:

438122, 438123

Abstract:

A packaged power semiconductor device ( ) with voltage isolation between a metal backside ( ) and the terminals ( ) of the device. A direct-bonded copper (âDBCâ) substrate ( ) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die ( ) is soldered or otherwise mounted to a first metal layer ( ) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.

US Patent:

6583505, Jun 24, 2003

Filed:

Mar 13, 2002

Appl. No.:

10/099137

Inventors:

Kang Rim Choi - Cupertino CA

Assignee:

Ixys Corporation - Santa Clara CA

International Classification:

H01L 2304

US Classification:

257730, 257796, 257706, 257707

Abstract:

A packaged power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The substrate has a lower surface. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses the die and has a lower surface. A curved backside includes the lower surfaces of the plastic package and substrate.

US Patent:

6710463, Mar 23, 2004

Filed:

Sep 5, 2001

Appl. No.:

09/947415

Inventors:

Kang Rim Choi - Cupertino CA

Assignee:

IXYS Corporation - Santa Clara CA

International Classification:

H01L 2348

US Classification:

257782, 257784, 257735, 257706

Abstract:

A packaged power semiconductor device ( ) with voltage isolation between a metal backside ( ) and the terminals ( ) of the device. A direct-bonded copper (âDBCâ) substrate ( ) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die ( ) is soldered or otherwise mounted to a first metal layer ( ) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.

US Patent:

6727585, Apr 27, 2004

Filed:

Mar 13, 2002

Appl. No.:

10/099061

Inventors:

Kang Rim Choi - Cupertino CA

Assignee:

Ixys Corporation - Santa Clara CA

International Classification:

H01L 23124

US Classification:

257728, 257723, 257706

Abstract:

A power device compatible with an SOT 227 package standard. The device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The first conductive layer has been patterned to provide at least first and second conductive blocks. A semiconductor die is bonded to the first block of the first conductive layer of the substrate. A terminal lead is coupled to the second block of the first conductive layer of the substrate.

US Patent:

6731002, May 4, 2004

Filed:

Nov 13, 2001

Appl. No.:

09/992602

Inventors:

Kang Rim Choi - Cupertino CA

Assignee:

IXYS Corporation - Santa Clara CA

International Classification:

H01L 2346

US Classification:

257735, 257692

Abstract:

A radio frequency power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses and protects the semiconductor die. A plurality of leads extend outwardly from the plastic package. The leads have blade-like shapes.

US Patent:

7005734, Feb 28, 2006

Filed:

May 5, 2003

Appl. No.:

10/430818

Inventors:

Kang Rim Choi - Cupertino CA, US
Nathan Zommer - Los Altos CA, US

Assignee:

IXYS Corporation - Santa Clara CA

International Classification:

H01L 23/02

US Classification:

257686, 257688

Abstract:

A power device includes a semiconductor die having an upper surface and a lower surface. One or more terminals are coupled to the die. A first substrate is bonded to the upper surface of the die. The first substrate is configured to provide a first heat dissipation path. A second substrate is bonded to the lower surface of the die. The second substrate is configured to provide a second heat dissipation path.

US Patent:

7459659, Dec 2, 2008

Filed:

Apr 20, 2007

Appl. No.:

11/738381

Inventors:

Kyoung Wook Seok - Seoul, KR
Kang Rim Choi - Cupertino CA, US

Assignee:

IXYS Corporation - Santa Clara CA

International Classification:

H05B 6/10
H05B 6/44

US Classification:

219624, 219626, 219662, 219661, 363 2101

Abstract:

A heating circuit for heating a conductive bowl includes a voltage source; a first heating coil provided between first and second nodes and being configured to heat the conductive bowl; a second heating coil provided between the second node and a third node and being configured to heat the conductive bowl; first capacitor and first switch provided in parallel between the first node and a fourth node; and second capacitor and second switch provided in parallel between the third node and the fourth node. The first and second heating coils define a circle-like shape having a center. The first and second heating coils are configured to be aligned to each other if one of the first and second heating coils is moved with respect to a line extending through the center of the circle-like shape.