Kamal Joseph Koshy from Pflugerville, TX, age 51

Us Patents

Fast Cmos Adder With Null-Carry Look-Ahead
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US Patent:

6782406, Aug 24, 2004
Filed:

Jun 7, 2001
Appl. No.:

09/877805
Inventors:

Kamal J. Koshy - Sunnyvale CA
Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:

G06F 750
US Classification:

708710, 708713, 708714
Abstract:

A null-carry-lookahead adder is configured to generate and propagate a null-carry signal within and through blocks and groups of blocks within the adder. The null-carry signal terminates the effects of a carry input signal beyond the point at which the null-carry signal is generated. By forming rules for generating and propagating null-carry signals through blocks and groups of blocks within the adder, a maximum P-channel stack depth of two can be achieved for a four-bit adder block, thereby substantially improving the speed of the null-carry-lookahead adder, compared to a convention carry-lookahead adder that is based on generating and propagating carry signals within the adder.

Method And Apparatus For Calculating Cyclic Redundancy Check (Crc) On Data Using A Programmable Crc Engine
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US Patent:

7171604, Jan 30, 2007
Filed:

Dec 30, 2003
Appl. No.:

10/749128
Inventors:

Jaroslaw J. Sydir - San Jose CA, US
Alok J Mathur - Milpitas CA, US
Wajdi Feghali - Boston MA, US
Kamal J. Koshy - Milpitas CA, US
Eduard Lecha - Fremont CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03M 13/00
US Classification:

714758
Abstract:

Configurable CRC calculation engines and methods of performing CRC calculations are presented. The configurable CRC calculation engines calculate a CRC value for the data using an associated polynomial and remainder. The method includes receiving a polynomial, receiving a block of data to determine a CRC value for, and calculating a CRC value for the data using the polynomial. With such devices and methods, the configurable CRC calculation engines are useful in various applications and protocols.

Apparatus And Method For Implementing The Kasumi Ciphering Process
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US Patent:

7433469, Oct 7, 2008
Filed:

Apr 27, 2004
Appl. No.:

10/833967
Inventors:

Kamal J. Koshy - Milpitas CA, US
Jaroslaw J. Sydir - San Jose CA, US
Wajdi K. Feghali - Boston MA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H04L 1/00
US Classification:

380 28, 380 37
Abstract:

An arrangement is provided for performing the KASUMI ciphering process. The arrangement includes apparatuses and methods that parallelize computations of two FI functions in KASUMI rounds within one clock cycle and computes two consecutive FL functions in the KASUMI rounds within one clock cycle.

Method And Apparatus For Scheduling The Processing Of Commands For Execution By Cryptographic Algorithm Cores In A Programmable Network Processor
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US Patent:

7512945, Mar 31, 2009
Filed:

Dec 29, 2003
Appl. No.:

10/747852
Inventors:

Jaroslaw J. Sydir - San Jose CA, US
Chen-Chi Kuo - Pleasanton CA, US
Kamal J. Koshy - Milpitas CA, US
Wajdi Feghali - Boston MA, US
Bradley A. Burres - Cambridge MA, US
Gilbert M. Wolrich - Framingham MA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 9/46
US Classification:

718100
Abstract:

A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.

Method And Apparatus For Aligning Ciphered Data
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US Patent:

7529924, May 5, 2009
Filed:

Dec 30, 2003
Appl. No.:

10/749035
Inventors:

Jaroslaw Sydir - San Jose CA, US
Kamal J. Koshy - Milpitas CA, US
Wajdi Feghali - Boston MA, US
Bradley A. Burres - Cambridge MA, US
Gilbert M. Wolrich - Framingham MA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H04L 9/00
US Classification:

713153, 713160, 713189, 726 11, 726 12
Abstract:

A data processing device includes a crypto unit having an alignment buffer for providing data to transmit buffer elements of a media switch fabric in multiples of a predetermined number of bytes. Ciphered data for a packet can be split over first and second transmit buffer elements so as to reduce the amount of software intervention.

Method And Apparatus For Performing Montgomery Multiplications
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US Patent:

7539718, May 26, 2009
Filed:

Sep 16, 2004
Appl. No.:

10/944354
Inventors:

Kamal J. Koshy - San Jose CA, US
Gilbert Wolrich - Framingham MA, US
Jaroslaw J. Sydir - San Jose CA, US
Wajdi K. Feghali - Boston MA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 7/38
US Classification:

708491
Abstract:

An arrangement is provided for performing Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e. g. , carry-save additions), and is performed by a Montgomery multiplication engine (MME). Basic operations in each iteration may be performed by multiple Montgomery multiplication processing elements (MMPEs). An MME may be arranged to pipeline the process of performing iterations of multiple basic operations and other operations required to complete a Montgomery multiplication both horizontally and vertically. An MME may also be arranged to interleave processes of performing two Montgomery multiplications.

Method And Apparatus For Performing An Authentication After Cipher Operation In A Network Processor
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US Patent:

7543142, Jun 2, 2009
Filed:

Dec 19, 2003
Appl. No.:

10/741676
Inventors:

Jaroslaw J. Sydir - San Jose CA, US
Kamal J. Koshy - Milpitas CA, US
Wajdi Feghali - Boston MA, US
Bradley A. Burres - Cambridge MA, US
Gilbert M. Wolrich - Framingham MA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H04L 9/00
US Classification:

713161
Abstract:

A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.

Apparatus And Method For Performing Md5 Digesting
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US Patent:

7627764, Dec 1, 2009
Filed:

Jun 25, 2004
Appl. No.:

10/877464
Inventors:

Kamal J. Koshy - Milpitas CA, US
Jaroslaw J. Sydir - San Jose CA, US
Wajdi K. Feghali - Boston MA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H04L 9/00
US Classification:

713181, 713161, 713168, 713175, 713189, 380251, 380259, 380260, 380 29, 709206, 709225
Abstract:

An arrangement is provided for performing MD5 digesting. The arrangement includes apparatuses and methods that pipeline the MD5 digesting process to produce a 128 bit digest for an input message of any arbitrary length.

Resumes

Senior Director

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Location:

6883 Alden Dr, Orchard Lake, MI 48324

Industry:

Telecommunications

Work:

Dell Technologies Jan 2018 - Oct 2019
Director
Charter Communications Jan 2018 - Oct 2019
Senior Director
Dell Technologies Jun 2015 - Dec 2017
Senior Principal Engineer
Hyperdense Networks Jul 2014 - Jun 2015
Co Founder
Intel Corporation 2005 - Jul 2014
Senior Manager and Architect

Education:

Stanford University 1999 - 2005
The University of Texas at Dallas 1995 - 1997
Master of Science, Masters, Electrical Engineering Indian Institute of Technology, Madras 1991 - 1995

Skills:

Soc
Asic
Processors
Semiconductors
Wireless
System Architecture
Embedded Systems
Vlsi
Verilog
Fpga
Debugging
Rtl Design
Hardware Architecture
Bluetooth
Microprocessors
Wifi
Digital Signal Processors
Firmware
Lte
Wimax
Integrated Circuit Design
Computer Architecture
Wireless Technologies
C++
Systemverilog
Application Specific Integrated Circuits
System on A Chip
Management
Technical Leadership
Start Ups
Entrepreneurship
Html
Css
Python

Languages:

English
Hindi

Certifications:

Machine Learning