Junting Liu

US Patent:

7915168, Mar 29, 2011

Filed:

Mar 10, 2010

Appl. No.:

12/721398

Inventors:

Junting Liu - Manassas VA, US
Er-Xuan Ping - Fremont CA, US
Seiichi Takedai - Bristow VA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/302

US Classification:

438689

Abstract:

Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

US Patent:

8440567, May 14, 2013

Filed:

Feb 23, 2011

Appl. No.:

13/033268

Inventors:

Junting Liu - Manassas VA, US
Er-Xuan Ping - Fremont CA, US
Seiichi Takedai - Bristow VA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/302

US Classification:

438689

Abstract:

Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

US Patent:

20050196971, Sep 8, 2005

Filed:

Jan 26, 2005

Appl. No.:

11/043724

Inventors:

Soovo Sen - Sunnyvale CA, US
Mark Fodor - Redwood City CA, US
Visweswaren Sivaramakrishnan - Santa Clara CA, US
Junting Liu - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L021/76
H01L021/31
H01L021/469

US Classification:

438778000

Abstract:

Embodiments in accordance with the present invention relate to various techniques which may be employed alone or in combination, to reduce or eliminate the deposition of material on the bevel of a semiconductor workpiece. In one approach, a shadow ring overlies the edge of the substrate to impede the flow of gases to bevel regions. The geometric feature at the edge of the shadow ring directs the flow of gases toward the wafer in order to maintain thickness uniformity across the wafer while shadowing the edge. In another approach, a substrate heater/support is configured to flow purge gases to the edge of a substrate being supported. These purge gases prevent process gases from reaching the substrate edge and depositing material on bevel regions.

US Patent:

20080152838, Jun 26, 2008

Filed:

Oct 23, 2007

Appl. No.:

11/877313

Inventors:

SOOVO SEN - Sunnyvale CA, US
MARK A. FODOR - Redwood City CA, US
VISWESWAREN SIVARAMAKRISHNAN - Santa Clara CA, US
JUNTING LIU - San Jose CA, US

Assignee:

APPLIED MATERIALS, INC. - Santa Clara CA

International Classification:

H05H 1/24

US Classification:

427569

Abstract:

Embodiments in accordance with the present invention relate to various techniques which may be employed alone or in combination, to reduce or eliminate the deposition of material on the bevel of a semiconductor workpiece. In one approach, a shadow ring overlies the edge of the substrate to impede the flow of gases to bevel regions. The geometric feature at the edge of the shadow ring directs the flow of gases toward the wafer in order to maintain thickness uniformity across the wafer while shadowing the edge. In another approach, a substrate heater/support is configured to flow purge gases to the edge of a substrate being supported. These purge gases prevent process gases from reaching the substrate edge and depositing material on bevel regions.

US Patent:

20090258485, Oct 15, 2009

Filed:

Apr 11, 2008

Appl. No.:

12/101332

Inventors:

Junting Liu - Manassas VA, US
Er-Xuan Ping - Fremont CA, US
Seiichi Takedai - Bristow VA, US

International Classification:

H01L 21/44

US Classification:

438612, 257E21476

Abstract:

Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.