Joonho Kim

US Patent:

7042785, May 9, 2006

Filed:

Dec 19, 2003

Appl. No.:

10/739071

Inventors:

Joonho Kim - Cary NC, US

Assignee:

Infineon Technologies, AG - Munich

International Classification:

G11C 7/00

US Classification:

365222, 365201

Abstract:

According to the present invention, refresh operation of a device employing a plural refresh cycle scheme is controlled. The refresh scheme employed by the device performs a plurality of refresh cycles of a predetermined quantity in response to a command initiating a refresh operation to maintain data storage. The present invention includes a mode generator that supplies information relating to a desired quantity of refresh cycles to be performed in response to the refresh initiating command and a refresh enable unit that controls the device to perform the desired quantity of refresh cycles within the refresh scheme in response to the refresh initiating command.

US Patent:

7187221, Mar 6, 2007

Filed:

Jun 30, 2004

Appl. No.:

10/881598

Inventors:

Joonho Kim - Cary NC, US
Jung Pill Kim - Cary NC, US
Alessandro Minzoni - Morrisville NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03K 3/017
H03L 7/06

US Classification:

327175, 327172, 327158, 327149, 327144

Abstract:

A method for adjusting the relative phases of two signals includes receiving first and second signals, which may, for example, be derived from a differential clock signal. A duty cycle error between the first signal and the second signal is detected by comparing a phase component of the first signal with a phase component of the second signal. This duty cycle error can then be corrected by delaying the second signal by an amount based upon a result derived from the comparing.

US Patent:

7221204, May 22, 2007

Filed:

Feb 1, 2005

Appl. No.:

11/048185

Inventors:

Jung Pill Kim - Cary NC, US
Joonho Kim - Cary NC, US
Alessandro Minzoni - Morrisville NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03K 3/017

US Classification:

327175, 327291

Abstract:

A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal and an inverted clock signal and to obtain a delay signal that indicates a time difference between transitions of the clock signal and the inverted clock signal. The second circuit is configured to receive the clock signal and the inverted clock signal and the delay signal and to delay the clock signal based on the delay signal to provide an output clock signal having substantially a 50% duty cycle.

US Patent:

7230465, Jun 12, 2007

Filed:

Jan 10, 2005

Appl. No.:

11/032459

Inventors:

Joonho Kim - Cary NC, US
Jung Pill Kim - Cary NC, US
Jonghee Han - Cary NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03K 3/017

US Classification:

327175, 327239

Abstract:

A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a first phase and a second phase and to obtain a first threshold value based on the length of the first phase and part of the second phase and provide a first pulse and response to the first threshold value. The second circuit is configured to receive the clock signal and to obtain a second threshold value based on the length of the second phase and part of the first phase and provide a second pulse in response to the second threshold value. The time between the start of the first pulse and the start of the second pulse is substantially one half clock cycle.

US Patent:

7304517, Dec 4, 2007

Filed:

May 30, 2006

Appl. No.:

11/442842

Inventors:

Joonho Kim - Cary NC, US
Jung Pill Kim - Cary NC, US
Jonghee Han - Cary NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03K 3/017

US Classification:

327175, 327166

Abstract:

A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal. The second circuit is configured to change the charge flow at a second transition of the clock signal. The first circuit and the second circuit are configured to change the charge flow in response to obtaining the threshold value.

US Patent:

20050128837, Jun 16, 2005

Filed:

Dec 16, 2003

Appl. No.:

10/738349

Inventors:

Joonho Kim - Cary NC, US

International Classification:

G11C007/00

US Classification:

365203000

Abstract:

Embodiments of the present invention are illustrated in a random access memory. In one embodiment, the random access memory includes memory banks and precharge timers configured to provide precharge signals to the memory banks. Each of the precharge timers corresponds to one of the memory banks and each of the precharge timers is configured to provide one of the precharge signals to the corresponding one of the memory banks in normal mode and in test mode.

US Patent:

20070080731, Apr 12, 2007

Filed:

Oct 11, 2005

Appl. No.:

11/247538

Inventors:

Jung Kim - Cary NC, US
Alessandro Minzoni - Morrisville NC, US
Joonho Kim - Cary NC, US

International Classification:

H03K 3/017

US Classification:

327175000

Abstract:

A duty cycle corrector includes a first controllable delay configured to delay a first signal to provide a second signal, a second controllable delay configured to delay the second signal to provide a third signal, a first fixed delay configured to delay the second signal to provide a fourth signal, a second fixed delay configured to delay the first signal to provide a fifth signal, and a circuit configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the fifth signal.