John M Scharr

US Patent:

6970662, Nov 29, 2005

Filed:

Dec 22, 2003

Appl. No.:

10/707576

Inventors:

Fan Shi - Penfield NY, US
John M. Scharr - Canandaigua NY, US
Mark A. Scheuer - Williamson NY, US
Patricia J. Donaldson - Pittsford NY, US

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G03G015/02

US Classification:

399 50

Abstract:

Systems and methods for measuring and setting grid voltages in an image forming device may include setting a first charging device of a first image forming station to a first voltage level and setting a second charging device of the first image forming station to be off; charging a charge-retentive surface with the first charging device set at the first voltage level; measuring and the charge imparted to the charge-retentive surface by the first charging device; storing the measured charge value. Systems and methods may further include repeating the setting, charging, measuring and storing steps for the first charging device for at least one additional voltage level; and determining at least one parameter of the first charging device based on the stored measured charge values for the first charging device for each voltage level.

US Patent:

49909584, Feb 5, 1991

Filed:

Dec 26, 1989

Appl. No.:

7/456399

Inventors:

Grace T. Brewington - Fairport NY
John M. Scharr - Farmington NY

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G03G 1506
G03G 2100

US Classification:

355245

Abstract:

A single component development system utilizing insulative nonmagnetic toner. A toner mover transports toner from a supply of toner for transfer to a donor roll from which it is deposited on to latent electrostatic images contained on an imaging surface. An electrically biased flap of conductive material is supported for rubbing contact with the surface of the toner mover. Supporting the electrically biased, conductive flap in rubbing contact with the toner mover results in effective reloading of the doner roll notwithstanding the presence a high stress condition such as the requirement for developing images containing conditnuous solid areas.

US Patent:

20180268916, Sep 20, 2018

Filed:

Mar 17, 2017

Appl. No.:

15/462397

Inventors:

- NORWALK CT, US
Kamran Uz Zaman - Pittsford NY, US
Christopher P. Caporale - Rochester NY, US
Jimmy E. Kelly - Rochester NY, US
John M. Scharr - Canandaigua NY, US
Alberto Rodriguez - Webster NY, US
Dennis J. Prosser - Walworth NY, US

Assignee:

XEROX CORPORATION - NORWALK CT

International Classification:

G11C 29/10
G11C 11/22
G06F 3/06

Abstract:

A method for ensuring that a memory array such as a ferroelectric memory array is properly electrically connected. The method may be performed, for example, prior to a read or write cycle, during functional testing of the memory array, etc. In one implementation, the memory array is read and the data set including a data bit from each cell is stored in a register. A solid logic 0's pattern is written into the memory array, and each cell is read. If no cell returns a logic 1, it is determined that the memory array is properly connected and the register data values are written to the memory array. If one or more cells returns a logic 1, it is determined that the memory array is improperly connected, the register data values are written to the memory array, and the memory array is removed and reinstalled.

US Patent:

20170235939, Aug 17, 2017

Filed:

Feb 16, 2016

Appl. No.:

15/044406

Inventors:

- Norwalk CT, US
Alberto Rodriguez - Webster NY, US
Scott Jonathan Bell - Rochester NY, US
John M. Scharr - Canandaigua NY, US

International Classification:

G06F 21/44
G06F 21/85

Abstract:

A component subsystem and a method for authenticating the component subsystem. The component subsystem may be installed in a host device. The method can include an authentication protocol, wherein the host device sends a test voltage value to the component subsystem which, in turn, generates a test voltage based on the test voltage value. The test voltage is applied to a test cell that includes a wordline, a bitline, and a memory film. A response voltage is read from the bitline and compared to an expected value. If the response voltage matches the expected value, host device and/or component subsystem functionality is enabled. If the response voltage does not match the expected value, the host device and/or component subsystem functionality is disabled.