Jinho Kim

US Patent:

20230101585, Mar 30, 2023

Filed:

Jan 14, 2022

Appl. No.:

17/576754

Inventors:

- San Jose CA, US
JINHO KIM - Saratoga CA, US
CYNTHIA FUNG - San Jose CA, US
GILLES FESTES - Fuveau, FR
BERNARD BERTELLO - Greasque, FR
PARVIZ GHAZAVI - San Jose CA, US
BRUNO VILLARD - Aix en Provence, FR
JEAN FRANCOIS THIERY - Caromb, FR
CATHERINE DECOBERT - Pourrieres, FR
SERGUEI JOURBA - Ailx En Provence, FR
FAN LUO - Fremont CA, US
LATT TEE - San Francisco CA, US
NHAN DO - Saratoga CA, US

International Classification:

G11C 29/50

Abstract:

A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC for the memory cells and a first number N of the memory cells having the lowest read current RC. A second read operation is performed to determine a second number N of the memory cells having a read current not exceeding a target read current RC. The target read current RC is equal to the lowest read current RC plus a predetermined current value. The die is determined to be acceptable if the second number N is determined to exceed the first number N plus a predetermined number. The die is determined to be defective if the second number N is determined not to exceed the first number N plus the predetermined number.

US Patent:

20210272973, Sep 2, 2021

Filed:

Feb 27, 2020

Appl. No.:

16/803876

Inventors:

- San Jose CA, US
Xian Liu - Sunnyvale CA, US
JinHo Kim - Saratoga CA, US
Serguei Jourba - Aix En Provence, FR
Catherine Decobert - Pourrieres, FR
Nhan Do - Saratoga CA, US

International Classification:

H01L 27/11534
H01L 27/11521

Abstract:

A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.

US Patent:

20200176459, Jun 4, 2020

Filed:

Dec 3, 2018

Appl. No.:

16/208150

Inventors:

- San Jose CA, US
JINHO KIM - Saratoga CA, US
XIAN LIU - Sunnyvale CA, US
SERGUEI JOURBA - Aix En Provence, FR
CATHERINE DECOBERT - Pourrieres, FR
NHAN DO - Saratoga CA, US

International Classification:

H01L 27/11521
H01L 27/11526
H01L 27/11531
H01L 29/10
H01L 29/423
H01L 29/78
H01L 29/788
H01L 21/28
H01L 29/66

Abstract:

A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.

US Patent:

20200176578, Jun 4, 2020

Filed:

Dec 3, 2018

Appl. No.:

16/208288

Inventors:

- San Jose CA, US
Catherine Decobert - Pourrieres, FR
Feng Zhou - Fremont CA, US
Jinho Kim - Saratoga CA, US
Xian Liu - Sunnyvale CA, US
Nhan Do - Saratoga CA, US

International Classification:

H01L 29/423
H01L 29/78
H01L 29/08
H01L 29/10
H01L 27/11521
H01L 29/66
G11C 16/04
G11C 16/10
G11C 16/14
G11C 16/26
H01L 29/788

Abstract:

A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.

US Patent:

20200013786, Jan 9, 2020

Filed:

Jul 5, 2018

Appl. No.:

16/028244

Inventors:

- San Jose CA, US
CATHERINE DECOBERT - Pourrieres, FR
FENG ZHOU - Fremont CA, US
JINHO KIM - Saratoga CA, US
XIAN LIU - Sunnyvale CA, US
NHAN DO - Saratoga CA, US

International Classification:

H01L 27/11524
H01L 29/66
H01L 29/423
H01L 29/78
H01L 29/788
H01L 21/266
H01L 21/768
H01L 21/8234
H01L 21/8238
H01L 27/088

Abstract:

A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

US Patent:

20200013788, Jan 9, 2020

Filed:

May 24, 2019

Appl. No.:

16/422740

Inventors:

- San Jose CA, US
Catherine Decobert - Pourrieres, FR
Feng Zhou - Fremont CA, US
Jinho Kim - Saratoga CA, US
Xian Liu - Sunnyvale CA, US
Nhan Do - Saratoga CA, US

International Classification:

H01L 27/11524
H01L 29/66
H01L 21/8238
H01L 21/8234
H01L 21/768
H01L 27/088
H01L 21/266
H01L 29/788
H01L 29/78
H01L 29/423

Abstract:

A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first fin, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

US Patent:

20200013789, Jan 9, 2020

Filed:

Sep 20, 2019

Appl. No.:

16/578104

Inventors:

- San Jose CA, US
Jinho Kim - Saratoga CA, US
Xian Liu - Sunnyvale CA, US
Serguei Jourba - Aix En Provence, FR
Catherine Decobert - Pourrieres, FR
Nhan Do - Saratoga CA, US

International Classification:

H01L 27/11531
H01L 29/423
H01L 29/10
H01L 29/66
H01L 27/11521
H01L 29/78
H01L 29/788

Abstract:

A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

US Patent:

20190326305, Oct 24, 2019

Filed:

Apr 19, 2018

Appl. No.:

15/957615

Inventors:

- San Jose CA, US
Jinho Kim - Saratoga CA, US
Xian Liu - Sunnyvale CA, US
Serguei Jourba - Aix En Provence, FR
Catherine Decobert - Pourrieres, FR
Nhan Do - Saratoga CA, US

International Classification:

H01L 27/11531
H01L 27/11521
H01L 29/10
H01L 29/423
H01L 29/78
H01L 29/788
H01L 29/66

Abstract:

A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.