Jeong Kyoo Choi

US Patent:

6407008, Jun 18, 2002

Filed:

May 5, 2000

Appl. No.:

09/564786

Inventors:

Yingbo Jia - Fremont CA
Long-Ching Wang - Cupertino CA
Jeong Yeol Choi - Palo Alto CA
Guo-Qiang (Patrick) Lo - Portland OR

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

H01L 21314

US Classification:

438773, 438758, 438769, 438770, 438774, 438775

Abstract:

Methods for forming nitrided oxides in semiconductor devices by rapid thermal oxidation, in which a semiconductor substrate having an exposed silicon surface is placed into a thermal process chamber. Then, an ambient gas comprising N O and an inert gas such as argon or N is introduced into the process chamber. Next, the silicon surface is heated to a predefined process temperature, thereby oxidizing at least a portion of the silicon surface. Finally, the semiconductor substrate is cooled. An ultra-thin oxide layer with uniform oxide characteristics, such as more boron penetration resistance, good oxide composition and thickness uniformity, increased charge to breakdown voltage in the oxide layer, can be formed.

US Patent:

6496399, Dec 17, 2002

Filed:

Aug 28, 2001

Appl. No.:

09/941372

Inventors:

Jeong Yeol Choi - Palo Alto CA
Sang-Yun Lee - Beaverton OR

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G11C 1500

US Classification:

365 49, 365168, 36518907

Abstract:

A ternary CAM system includes a main memory cell configured to store complementary data signals D/D#. A first transistor has a source coupled to receive data signal D#, and a gate coupled to receive a compare signal C. A second transistor has a source coupled to receive data signal D, and a gate coupled to receive complementary compare signal C#. A third transistor has a gate coupled to drain regions of the first and second transistors. A mask cell storing a mask value is coupled to the source of the third transistor. A pre-charged match line is coupled to the drain of the third transistor. If compare signals C/C# match data signals D/D#, then the third transistor is turned off, thereby isolating match line and mask cell. If compare signals C/C# dont match data signals D/D#, then the third transistor is turned on, thereby coupling mask cell and match line.

US Patent:

7292968, Nov 6, 2007

Filed:

Apr 11, 2001

Appl. No.:

09/832933

Inventors:

Lifeng Wu - Fremont CA, US
Zhihong Liu - Cupertino CA, US
Alvin I. Chen - San Jose CA, US
Jeong Y. Choi - Portland OR, US
Bruce W. McGaughy - Fremont CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/44

US Classification:

703 13, 717135

Abstract:

The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described. To further improve the circuit reliability simulation, a gradual or multi-step aging is used instead of the standard one step aging process.

US Patent:

7835890, Nov 16, 2010

Filed:

Oct 4, 2007

Appl. No.:

11/867554

Inventors:

Lifeng Wu - Fremont CA, US
Zhihong Liu - Cupertino CA, US
Alvin I. Chen - San Jose CA, US
Jeong Y. Choi - Portland OR, US
Bruce W. McGaughy - Fremont CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/44

US Classification:

703 2, 703 14, 703 17, 717124, 324719

Abstract:

The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described. To further improve the circuit reliability simulation, a gradual or multi-step aging is used instead of the standard one step aging process.

US Patent:

7894270, Feb 22, 2011

Filed:

Feb 11, 2009

Appl. No.:

12/378248

Inventors:

Jeong Y. Choi - Palo Alto CA, US
Stephen Fung - Cupertino CA, US

Assignee:

MoSys, Inc. - Santa Clara CA

International Classification:

G11C 16/06

US Classification:

36518525, 36518509, 36518521

Abstract:

A method and apparatus for selectively restoring data in a non-volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data. The manner in which data is restored will depend on whether the data changed because of an erase failure or a program failure. If only a program failure occurred then the data will be reprogrammed without an intervening erase step. If the data experienced an erase failure, then the data will be erased prior to being programmed with correct data.

US Patent:

8238169, Aug 7, 2012

Filed:

Feb 15, 2011

Appl. No.:

13/027621

Inventors:

Jeong Y. Choi - Palo Alto CA, US
Stephen Fung - Cupertino CA, US

Assignee:

MoSys, Inc. - Santa Clara CA

International Classification:

G11C 16/06

US Classification:

36518525, 36518509, 36518521

Abstract:

A method and apparatus for selectively restoring data in a non-volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data. The manner in which data is restored will depend on whether the data changed because of an erase failure or a program failure. If only a program failure occurred then the data will be reprogrammed without an intervening erase step. If the data experienced an erase failure, then the data will be erased prior to being programmed with correct data.

US Patent:

8361863, Jan 29, 2013

Filed:

Nov 13, 2008

Appl. No.:

12/291765

Inventors:

Jeong Y. Choi - Palo Alto CA, US

Assignee:

MoSys, Inc. - Santa Clara CA

International Classification:

H01L 21/336

US Classification:

438258, 438250, 438251, 438252, 438255, 438257

Abstract:

A method of forming an embedded DRAM cell having multiple-thickness gate dielectrics. An oxidation-enhancing dopant is selectively implanted into a well region in an area that is exposed by a first mask. A thermal oxidation step simultaneously produces the field dielectric for two distinct devices each having a different oxide thickness. The method is applicable to quad-density DRAM cells using fewer oxidation steps. The method is also applicable to planar DRAM cells, and does not require increasing the number of masks during the fabrication of planar DRAM cells.

US Patent:

8460995, Jun 11, 2013

Filed:

Jul 30, 2010

Appl. No.:

12/804855

Inventors:

Jeong Y. Choi - Palo Alto CA, US

Assignee:

MoSys, Inc. - Santa Clara CA

International Classification:

H01L 21/8242

US Classification:

438239

Abstract:

An embedded memory system includes an array of random access memory (RAM) cells, on the same substrate as an array of logic transistors. Each RAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The embedded RAM system includes fewer metal layers in the memory region than in the logic region.