Jeffrey Charles Haines

US Patent:

6376350, Apr 23, 2002

Filed:

Feb 23, 2001

Appl. No.:

09/792766

Inventors:

Michael P. Duane - Round Rock TX
Jeffrey C. Haines - Austin TX
Frederick N. Hause - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 213205

US Classification:

438592, 438299

Abstract:

The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon and forming a recess in the layer of polysilicon. The method further comprises forming a metal region in the recess and patterning the layer of polysilicon to define a gate stack comprised of the metal region and the layer of polysilicon.

US Patent:

6579801, Jun 17, 2003

Filed:

Nov 30, 2001

Appl. No.:

09/997986

Inventors:

Christoph Schwan - Gebhardshain, DE
Jeffrey C. Haines - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21311

US Classification:

438700, 438723, 438724

Abstract:

Various methods of fabricating substrate trenches and isolation structures therein are disclosed. In one aspect, a method of fabricating a trench in a substrate is provided. An oxide/nitride stack is formed on the substrate. An opening with opposing sidewalls is plasma etched in the silicon nitride film until a first portion of the oxide film is exposed while second and third portions of the oxide film positioned on opposite sides of the first portion remain covered by first and second portions of the silicon nitride film that project inwardly from the opposing sidewalls. The oxide film is etched for a selected time period in order to expose a portion of the substrate and to define first and second oxide/nitride ledges that project inwardly from the opposing sidewalls. The substrate is etched to form the trench with the first and second oxide/nitride ledges protecting underlying portions of the substrate.

US Patent:

6613688, Sep 2, 2003

Filed:

Apr 26, 2002

Appl. No.:

10/133061

Inventors:

Thomas M. Brown - Austin TX
Edward O. Travis - Austin TX
Jeffrey C. Haines - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438710, 451 41, 438692

Abstract:

A model-based approach for generating an etch pattern to decrease topographical uniformity involves placing reverse dummy features ( ) in a region of a semiconductor substrate ( ) according to the topography of the region and adjacent regions. The reverse dummy features are placed inconsistently over the semiconductor substrate ( ) because the need for reverse dummy features is inconsistent and varies from design to design. In one embodiment, the reverse dummy features ( ) having varying widths are placed with varying spacing between them and are placed in different regions. The determination of location, size and spacing of the reverse dummy features ( ) is determined based upon the uniformity effect over the entire semiconductor die and may be used in conjunction with the placement of printed dummy features. After placing the reverse dummy features ( ), a planarization process may be performed to remove the reverse dummy features, which improves the planarization.

US Patent:

7220655, May 22, 2007

Filed:

Dec 17, 2001

Appl. No.:

10/023347

Inventors:

Frederick N. Hause - Austin TX, US
Jeffrey C. Haines - Austin TX, US
Michael E. Exterkamp - Pflugerville TX, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438424, 438427, 438405

Abstract:

Disclosed herein is a method comprised of providing a wafer comprised of a bulk substrate, an insulating layer positioned above the bulk substrate, and a semiconducting layer positioned above the insulating layer, forming an opening in the semiconducting layer and the insulating layer to thereby expose a surface area of the bulk substrate, forming an alignment mark in the bulk substrate within the exposed surface area of the bulk substrate, and forming a layer of material above the alignment mark and in the opening. A wafer is also disclosed herein that is comprised of a bulk substrate, an insulating layer positioned above the bulk substrate, a semiconducting layer positioned above the insulating layer, an opening formed in the semiconducting layer and the insulating layer, an alignment mark formed in the bulk substrate within an area defined by the opening, and a layer of material positioned above the alignment mark and within the opening.

US Patent:

7494749, Feb 24, 2009

Filed:

Feb 22, 2005

Appl. No.:

11/064431

Inventors:

Jeffrey C. Haines - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G03F 9/00

US Classification:

430 5, 430313, 430323, 430329, 430330, 430394

Abstract:

The invention, in its various aspects, is an interdependent binary photomask for use in a photolithography operation in a semiconductor fabrication process, a method for fabricating these interdependent photomasks, and a method of using the same. The photomask comprises a first binary reticle and a second binary reticle. Each binary reticle includes a pattern formed on a plate, but the pattern formed on one plate is interdependent with the pattern formed on the other plate so that the reticles are used in tandem to transfer the pattern onto wafers having features residing in different focal planes. The method of fabricating the interdependent binary photomask consequently includes specifying a first and a second portion of a circuit layout, the first and second circuit portions being interdependent. The first and second portions are digitized and used to form first and second interdependent patterns on separate reticles. In use, the first reticle is aligned with a portion of a wafer and the wafer portion is then exposed.