James N Keller

Author:

James Keller

ISBN #:

0262024071

Author:

James Keller

ISBN #:

0262112078

Author:

James Keller

ISBN #:

0262522152

Author:

James Keller

ISBN #:

0262581604

Author:

James Keller

ISBN #:

0262611368

Author:

James Keller

ISBN #:

0387245154

Author:

James Keller

ISBN #:

0818912324

Author:

James Keller

ISBN #:

0792385217

US Patent:

8219758, Jul 10, 2012

Filed:

Jul 10, 2009

Appl. No.:

12/500810

Inventors:

James Wang - Vista CA, US
Zongjian Chen - Palo Alto CA, US
James B. Keller - Redwood City CA, US
Timothy J. Millet - Mountain View CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711129, 711117, 711118, 711128, 711130, 711136, 711139, 711145, 711160

Abstract:

In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.

US Patent:

8244981, Aug 14, 2012

Filed:

Jul 10, 2009

Appl. No.:

12/500747

Inventors:

James Wang - Vista CA, US
Zongjian Chen - Palo Alto CA, US
James B. Keller - Redwood City CA, US
Timothy J. Millet - Mountain View CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/00

US Classification:

711128, 711117, 711118, 711129, 711130, 711136, 711139, 711145, 711160

Abstract:

In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

US Patent:

8392658, Mar 5, 2013

Filed:

Jul 10, 2009

Appl. No.:

12/500768

Inventors:

James Wang - Vista CA, US
Zongjian Chen - Palo Alto CA, US
James B. Keller - Redwood City CA, US
Timothy J. Millet - Mountain View CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/00

US Classification:

711128, 711118, 711130, 711133, 711136, 711141, 711146, 711147

Abstract:

In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

US Patent:

8566526, Oct 22, 2013

Filed:

Jul 10, 2012

Appl. No.:

13/545526

Inventors:

James Wang - Vista CA, US
Zongjian Chen - Palo Alto CA, US
James B. Keller - Redwood City CA, US
Timothy J. Millet - Mountain View CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 13/00

US Classification:

711129, 711117, 711170

Abstract:

In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.