James B Keller

Author:

James Keller

ISBN #:

0262024071

Author:

James Keller

ISBN #:

0262112078

Author:

James Keller

ISBN #:

0262522152

Author:

James Keller

ISBN #:

0262581604

Author:

James Keller

ISBN #:

0262611368

Author:

James Keller

ISBN #:

0387245154

Author:

James Keller

ISBN #:

0818912324

Author:

James Keller

ISBN #:

0792385217

US Patent:

6370621, Apr 9, 2002

Filed:

Dec 21, 1998

Appl. No.:

09/217699

Inventors:

James B. Keller - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

711141, 712 14, 712 16, 712 28

Abstract:

A messaging scheme that conserves system memory bandwidth during a memory read operation in a multiprocessing computer system is described. A source processing node sends a memory read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. The target node transmits a read response to the source node containing the requested data and also concurrently transmits a probe command to one or more of the remaining nodes in the multiprocessing computer system. In response to the probe command each remaining processing node checks whether the processing node has a cached copy of the requested data. If a processing node, other than the source and the target nodes, finds a modified cached copy of the designated memory location, that processing node responds with a memory cancel response sent to the target node and a read response sent to the source node. The read response contains the modified cache block containing the requested data, and the memory cancel response causes the target node to abort further processing of the memory read command, and to stop transmission of the read response, if the target node hasnt transmitted the read response yet. The memory cancel message thus attempts to avoid relatively lengthy and time-consuming system memory accesses when the system memory has a stale data.

US Patent:

6385705, May 7, 2002

Filed:

Oct 30, 2000

Appl. No.:

09/702147

Inventors:

James B. Keller - Palo Alto CA
Dale E. Gulick - Austin TX
Larry D. Hewitt - Austin TX
Geoffrey Strongin - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

711154, 709200, 709238, 711217

Abstract:

A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions.

US Patent:

6389526, May 14, 2002

Filed:

Aug 24, 1999

Appl. No.:

09/382360

Inventors:

James B. Keller - Palo Alto CA
Dale Gulick - Austin TX
Larry Hewitt - Austin TX
Geoffrey Strongin - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1316

US Classification:

712 30, 712 29, 712 40, 712227, 711141, 711145, 710268, 710264, 710306, 710 48, 710 36, 710 5

Abstract:

A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes each one of which is coupled to an individual memory. An I/O bridge coupled to a first circuit node is configured to generate non-coherent memory access command packets and non-coherent interrupt command packets. The first circuit node also generates a coherent interrupt command packet in response to receiving the non-coherent interrupt command packet. The first circuit node transmits the coherent interrupt command packet to another circuit node, possibly the second circuit node. However, the transmission of the coherent interrupt command packet may be delayed. Any delay in transmission is based on a comparison of the pipe identifications of the non-coherent command packets.

US Patent:

6393529, May 21, 2002

Filed:

Aug 10, 1999

Appl. No.:

09/370970

Inventors:

James B. Keller - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1208

US Classification:

711141, 709216, 711143, 711147, 712 28

Abstract:

A messaging scheme that conserves system memory bandwidth and maintains cache coherency during a victim block write operation in a multiprocessing computer system is described. A source node having a dirty victim cache blockâa modified cache block that is being written back to a corresponding system memoryâsends a victim block command along with the dirty cache block data to the target processing node having associated therewith the corresponding system memory. The target node responds with a target done message sent to the source node and also initiates a memory write cycle to transfer the received cache block to the corresponding memory location. If the source node encounters an invalidating probe between the time it sent the victim block command and the time it received the target done response, the source node sends a memory cancel response to the target node. The memory cancel response helps maintain cache coherency within the system by causing the target node to abort further processing of the memory write cycle involving the victim block because the victim block may no longer contain the valid data. The memory cancel response may also conserve the system memory bandwidth by attempting to avoid relatively lengthy memory write cycles when the victim block may represent stale data.

US Patent:

6393546, May 21, 2002

Filed:

Feb 16, 2001

Appl. No.:

09/788067

Inventors:

David B. Witt - Austin TX
James B. Keller - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1202

US Classification:

712 36, 711210

Abstract:

A register renaming apparatus includes one or more physical registers which may be assigned to store a floating point value, a multimedia value, an integer value and corresponding condition codes, or condition codes only. The classification of the instruction (e. g. floating point, multimedia, integer, flags-only) defines which lookahead register state is updated (e. g. floating point, integer, flags, etc. ), but the physical register can be selected from the one or more physical registers for any of the instruction types. Determining if enough physical registers are free for assignment to the instructions being selected for dispatch includes considering the number of instructions selected for dispatch and the number of free physical registers, but excludes the data type of the instruction. When a code sequence includes predominately instructions of a particular data type, many of the physical registers may be assigned to that data type (efficiently using the physical register resource). By contrast, if different sets of physical registers are provided for different data types, only the physical registers used for the particular data type may be used for the aforementioned code sequence.

US Patent:

6434640, Aug 13, 2002

Filed:

May 25, 1999

Appl. No.:

09/320134

Inventors:

James B. Keller - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 300

US Classification:

710 52, 710 29, 711167

Abstract:

A computer system employs a distributed set of links between processing nodes (each processing node including at least one processor). Each link includes a clock signal which is transmitted with and in the same direction as the signals carrying information on the link. The line carrying the clock signal may be matched to the information lines, controlling skew and transport time differences to allow for high frequency operation. Because the clock signals at a transmitter and a receiver may not have a common source, a receive buffer may be employed. Data transmitted across the link is stored into the receive buffer responsive to the transmitter clock signal (e. g. by maintaining a load pointer controlled according to the transmitter clock), and is removed from the buffer responsive to the receiver clock signal (e. g. by maintaining an unload pointer controlled according to the receiver clock). The buffer includes sufficient entries for data to account for clock uncertainties (e. g.

US Patent:

6473849, Oct 29, 2002

Filed:

Sep 17, 1999

Appl. No.:

09/398955

Inventors:

James B. Keller - Palo Alto CA
William A. Hughes - Burlingame CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1517

US Classification:

712 30, 712 29, 709229, 709210, 709216, 709226

Abstract:

A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. The microcode within the lock requesting node transmits a write command to write corresponding node identification data into a lock register in the arbitrating node. The lock requesting node iteratively reads the lock register until it finds its node identification data stored therein with a valid bit set. The lock requesting node then informs all remaining processing nodes to release shared system resources. This is accomplished through a release request bit and a release response bit in each processing node. After completion of lock operations, the lock requesting node sends a message to the arbitrating node to reset the valid bit in the lock register, and a broadcast message to each remaining node to reset the release request bit. In an alternate embodiment, each processing node includes a lock resource register instead of a release response bit.

US Patent:

6490661, Dec 3, 2002

Filed:

Dec 21, 1998

Appl. No.:

09/217212

Inventors:

James B. Keller - Palo Alto CA
Derrick R. Meyer - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1314

US Classification:

711150, 711141, 711130

Abstract:

A messaging scheme that accomplishes cache-coherent data transfers during a memory read operation in a multiprocessing computer system is described. A source processing node sends a read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. In response to the read command, the target processing node transmits a probe command to all the remaining processing nodes in the computer system regardless of whether one or more of the remaining nodes have a copy of the data cached in their respective cache memories. Probe command causes each node to maintain cache coherency by appropriately changing the state of the cache block containing the requested data and by causing the node having an updated copy of the cache block to send the cache block to the source node. Each processing node that receives a probe command sends, in return, a probe response indicating whether that processing node has a cached copy of the data and the state of the cached copy if the responding node has the cached copy. The target node sends a read response including the requested data to the source node.