James H Hsu
from Bethesda, MD
- Also known as:
-
- James Hsu
- James Campbell Estate
- James Hsien Tsung Hsu
- James Campbell Co Llc
- James Campbell Company Llc
- James Thsu
- Jeng Hsu
- James Su
- Hsien Hsu
- Phone and address:
-
6011 Mckinley St, Bethesda, MD 20817
301 564-1887
James Hsu Phones & Addresses
- 6011 Mckinley St, Bethesda, MD 20817 • 301 564-1887 • 301 564-4862 • 301 571-1958
- Rockville, MD
- Santa Barbara, CA
- Kapolei, HI
- 19627 Barclay Rd, Castro Valley, CA 94546 • 510 583-6226
Work
-
Address:404 Bryant St, San Francisco, CA 94107
Education
-
School / High School:Stanford University
Ranks
-
Licence:California - Active
-
Date:2001
Lawyers & Attorneys
James Chai-Hsian Hsu, San Francisco CA - Lawyer
view sourceAddress:
404 Bryant St, San Francisco, CA 94107
Licenses:
California - Active 2001
Education:
Stanford University
Columbia University School of Law
Columbia University School of Law
James Chai-hsiang Hsu, Redwood City CA - Lawyer
view sourceAddress:
209 Redwood Shores Pkwy, Redwood City, CA 94065
Experience:
26 years
Jurisdiction:
New York (1998)
Education:
Columbia University
Memberships:
New York State Bar (1998)
James Hsu - Lawyer
view sourceISLN:
913820832
Admitted:
1998
University:
Stanford University, B.A., 1992
Law School:
Columbia University, J.D., 1997
James Chai-Hsian Hsu, Redwood City CA - Lawyer
view sourceAddress:
209 Redwood Shores Pkwy, Redwood City, CA 94065
Phone:
650 628-1500 (Phone)
Experience:
23 years
Jurisdiction:
California (2001)
Law School:
Columbia Univ School of Law
Education:
Stanford Univ, Undergraduate Degree
Columbia Univ School of Law, Law Degree
Columbia Univ School of Law, Law Degree
Memberships:
California State Bar (2001)
License Records
James Hsu
License #:
12293 - Expired
Category:
Professional
Issued Date:
Oct 10, 1979
James Chien-Min Hsu
License #:
CA024661L - Expired
Category:
Accountancy
Type:
Certified Public Accountant
Us Patents
-
Method For Forming A Contoured Floating Gate Cell
view source -
US Patent:6413818, Jul 2, 2002
-
Filed:Oct 8, 1999
-
Appl. No.:09/415936
-
Inventors:Chin-Yi Huang - Pao Shan, TW
Chih-Jen Huang - Hsinchu County, TW
Yun Chang - Hsinchu County, TW
James Hsu - Saratoga CA
Samuel C. Pan - Hsinchu, TW -
Assignee:Macronix International Co., Ltd. - Hsinchu
-
International Classification:H01L 21336
-
US Classification:438257, 438263, 438270, 438593, 438594
-
Abstract:A floating gate having a first and second end region, each of which are positioned adjacent to a corresponding lateral end of the floating gate. A middle region is positioned laterally towards a middle of the floating gate relative to the first and second end regions. The first end region, the middle region and the second end region are formed of a same material during a single fabrication step, and the middle region formed has a thickness which is less than a thickness of the first or second end regions. This invention further includes a method for forming a contoured floating gate for use in a floating gate memory cell. The method includes forming a polysilicon layer over first and second spaced apart oxide structures and a floating gate region between the first and second oxide structures such that the polysilicon layer formed in the floating gate region has a first end region adjacent the first oxide structure, a second end region adjacent the second oxide structure, and a middle region positioned laterally between the first and second end regions. The method further includes removing a portion of the polysilicon layer in the floating gate region such that the vertical thickness of the first and second end regions remain greater than the vertical thickness of the middle region.
-
Semiconductor Structure With The Common Source Line
view source -
US Patent:6700165, Mar 2, 2004
-
Filed:Oct 25, 2002
-
Appl. No.:10/279795
-
Inventors:Po-An Chen - Hsinchu, TW
James Juen Hsu - Saratoga CA -
Assignee:Winbond Electronics Corporation - Hsinchu
-
International Classification:H01L 2976
-
US Classification:257390, 257392, 257393, 257391
-
Abstract:A semiconductor structure with common source line, the semiconductor structure has two word lines, some bit lines, a silicon-based layer and a suicide layer. The silicon-based layer is located between and electrically separated from these word lines, but is electrically coupled with these bit lines. The silicide layer is located over and electrically coupled with the silicon-based layer. Moreover, suicide layer and silicide layer could be replaced by a silicon-base conductor layer, and are directly electrically coupled with some separated doped regions that located inside a substrate.
-
Self-Aligned Dual-Floating Gate Memory Cell And Method For Manufacturing The Same
view source -
US Patent:6858501, Feb 22, 2005
-
Filed:Apr 14, 2003
-
Appl. No.:10/412293
-
Inventors:James Juen Hsu - Saratoga CA, US
-
Assignee:Winbond Electronics Corporation - Hsinchu
-
International Classification:H01L021/336
-
US Classification:438283, 438257
-
Abstract:An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.
-
Weak Programming Method Of Non-Volatile Memory
view source -
US Patent:6862219, Mar 1, 2005
-
Filed:Mar 19, 2003
-
Appl. No.:10/249140
-
Inventors:Shih-Hsien Yang - Hsinchu, TW
Chien-Min Wu - Hsinchu, TW
James Juen Hsu - Saratoga CA, US
Chi-Moon Huang - Hsinchu, TW -
Assignee:Winbond Electronics Corp. - Hsinchu
-
International Classification:G11C016/04
-
US Classification:36518528, 36518533
-
Abstract:A weak programming method of a non-volatile memory. A first voltage is applied to a substrate during a first duration, while a control-gate voltage, such as zero volt, is applied to the gate, such that the leakage of the bit line is reduced and electron-hole pairs are generated. In the second duration, a second voltage is applied to the substrate, and a third voltage is applied to the gate to enhance the capability of injecting electrons into the floating gate of the non-volatile memory. Therefore, the distribution of the threshold voltage is more concentrated. The second voltage has a polarity the same as that of the first voltage, while the polarity of the third voltage is opposite to that of the second voltage.
-
Reduced Video Player Start-Up Latency In Http Live Streaming And Similar Protocols
view source -
US Patent:8510460, Aug 13, 2013
-
Filed:Apr 29, 2011
-
Appl. No.:13/098286
-
Inventors:James Kong Hsu - Redwood City CA, US
-
Assignee:CBS Interactive Inc. - San Francisco CA
-
International Classification:G06F 15/16
-
US Classification:709231, 709236
-
Abstract:Technology for processing an ordered sequence of frames of a media program intended for play in an HTTP Live Streaming (HLS) player. Processing a first ordered subset of frames of the sequence. Processing a second ordered subset of frames of the sequence separate from the first subset. The second subset following on the first forms a third ordered subset of frames of the media program. Processing the second subset includes creating a manifest file of the subset. The playing time of processed frames of the first subset is at least equal to the processing time of the second subset. Processing the first subset can include creating a manifest file of the subset. The media program can include ads (at least a pre-roll ad) and content. The first ordered subset can be the pre-roll ad. The second ordered subset can be the content and remaining ads (e. g.
-
Startup Bitrate In Adaptive Bitrate Streaming
view source -
US Patent:8516144, Aug 20, 2013
-
Filed:Apr 29, 2011
-
Appl. No.:13/098236
-
Inventors:James Kong Hsu - Redwood City CA, US
-
Assignee:CBS Interactive Inc. - San Francisco CA
-
International Classification:G06F 15/16
-
US Classification:709231, 709232
-
Abstract:Streaming media at an adaptive bitrate streaming media player. Tracking a bitrate history of the player. Determining a startup bitrate from the bitrate history. Streaming at the determined bitrate. Tracking a bitrate history of the player can include storing tracked bitrates in a cookie accessible by the player; and determining a startup bitrate can include determining a startup bitrate from the cookie. Determining a startup bitrate can include determining an average tracked bitrate over the last N tracked bitrates. The average tracked bitrate can be weighted toward more recent tracked bitrates. Determining a startup bitrate can include determining a maximum startup bitrate. The bitrate history can include the maximum bitrate of the player over the last X sessions; and the maximum startup bitrate can be the lowest maximum bitrate over the last X sessions. The maximum startup bitrate can be the mode among maximum bitrates over the last X sessions.
-
Method Of Forming A Dual Local Oxidation Structure Of A Memory Chip In A Semiconductor Wafer
view source -
US Patent:20010014507, Aug 16, 2001
-
Filed:Jul 2, 1999
-
Appl. No.:09/345814
-
Inventors:JAMES JUEN HSU - SARATOGA CA, US
-
International Classification:H01L021/336
H01L021/8242 -
US Classification:438/298000, 438/297000, 438/241000, 438/258000
-
Abstract:The present invention provides a method of forming a dual local oxidation structure (LOCOS) of a memory circuit in a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and non-overlapping first and second areas defined on the surface of the silicon substrate. The first area is used for forming a memory array of the memory circuit and the second area is used for forming a peripheral circuit of the memory circuit for controlling the operation of the memory array. Using this method, a pad oxide layer and a silicon nitride layer are first formed on the silicon substrate. The silicon nitride layer has a plurality of recesses extending down to the surface of the silicon substrate. The widths of the recesses in the first area are narrower than the widths of the recesses in the second area. Then, a high temperature oxidation process is performed to form a field oxide layer on the surface of the silicon substrate within each of the recesses. This method makes the field oxide layer in each of the recesses in the first area thinner than the field oxide layer in each of the recesses in the second area.
-
Self-Aligned Dual-Floating Gate Memory Cell .
view source -
US Patent:20030107078, Jun 12, 2003
-
Filed:Feb 8, 2002
-
Appl. No.:10/067889
-
Inventors:James Hsu - Saratoga CA, US
-
Assignee:Winbond Electronics Corporation
-
International Classification:H01L029/788
-
US Classification:257/315000
-
Abstract:An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.
Resumes
James Hsu Columbus, IN
view sourceWork:
Altran - Valeo Sylvania
Seymour, IN
Jan 2013 to Jul 2013
Hardware Engineer Cummins
Columbus, IN
Aug 2011 to Nov 2012
Hardware Engineer Wattminder
Sunnyvale, CA
Dec 2010 to Jul 2011
Hardware Engineer-Volunteer Ferrotec
San Jose, CA
Nov 2007 to Oct 2009
Electrical Engineer Intel Corporation
Santa Clara, CA
Oct 2005 to Mar 2007
Manufacturing Engineer Intel - Kelly Services
Santa Clara, CA
Mar 2005 to Sep 2005
Manufacturing Technician
Seymour, IN
Jan 2013 to Jul 2013
Hardware Engineer Cummins
Columbus, IN
Aug 2011 to Nov 2012
Hardware Engineer Wattminder
Sunnyvale, CA
Dec 2010 to Jul 2011
Hardware Engineer-Volunteer Ferrotec
San Jose, CA
Nov 2007 to Oct 2009
Electrical Engineer Intel Corporation
Santa Clara, CA
Oct 2005 to Mar 2007
Manufacturing Engineer Intel - Kelly Services
Santa Clara, CA
Mar 2005 to Sep 2005
Manufacturing Technician
Education:
San Jose State University
San Jose, CA
2004 to 2007
MS in Electrical Engineering University of California, Riverside
Riverside, CA
2001 to 2003
BS in Electrical Engineering
San Jose, CA
2004 to 2007
MS in Electrical Engineering University of California, Riverside
Riverside, CA
2001 to 2003
BS in Electrical Engineering
Skills:
1. Ability to lead different aspects of electronics product from design to release phase thru processes such as: Analysis, DFMEAs, team meetings, supplier conference calls, problem solving meetings and design reviews. 2. PCB Circuits designing, testing and soldering. 3. Familiar with testing equipment including Oscilloscopes, Power Supplies(Linear&Switch-Mod... Multimeters, Soldering Irons, Signal Generators, ESD equipments. 4. Firmware programming(including Motorolla 8051, MSP430) and testing. 5. Experiences with various sensor interfaces, A/D and D/A interfaces, communicatin protocols, and state machines. 6. Linux system application and installation onto PC systems 7. Project Management Skills and Experiences. 8. Familiar with PID Control Algorithm. 9. Programming languages including C, C++, Matlab, Assembly, VHDL. 10. IDE including CCSV4 IDE. 11. National Instrument LabView and Labwindows CVI. 12. Circuit design EDAs from schematic to layout including Cadence Allegro/OrCAD, EAGLE, LTSPICE. 13. IC design tools from schematic to layout, including Virtuoso, Assura DRC/LVS, Affirma Analog Circuit Design Environment, PSPICE. 14. Able to read resistor color bands and circuit soldering. 15. Familiar with electronic component testing and analysis. 16. Operating systems including Windows Vista, Win7, Linux. 17. Application software including MS Excel, Power Point, Word, Outlook, Lotus Notes, Oracle, EPLM. 18. Knowledge in UL, CE, RoHS, EMI. 19. Good oral, written and interpersonal skills. 20. Ability to write specifications, testing plans, procedures, and reports. 21. Knowledge in fuel systems and temperature systems controls. 22. Experiences working with microprocessors including Freescale [] TI(16bits), Renesas(16bits). 23. Experiences working on designing switching and linear power supplies.
James Hsu San Francisco, CA
view sourceWork:
Foxconn Technology Group
Apr 2012 to Present
Senior Manager/Financial Planning & Analysis OASIS CAPITAL VENTURES, LLC
Danville, CA
Sep 2007 to Sep 2011
Senior Manager ADVANCED EQUITIES, INC
San Francisco, CA
Nov 2005 to Jun 2007
Vice President SAN FRANCISCO CENTER
San Francisco, CA
Oct 2001 to Sep 2005
Relationship Manager/Senior Financial Adviser STOCKWALK.COM/M.ONE INVESTMENT SECURITIES
San Francisco, CA
Aug 1995 to Oct 2001
Financial Consultant/Operation Manager/Trader INTERNATIONAL CHI MEI TRADING
South San Francisco, CA
Dec 1994 to Jul 1995
Account Executive/Marketing Specialist MONEY TREE GEM COMPANY
San Francisco, CA
Jun 1991 to Dec 1994
Sales Manager CAL BERKELEY FEDERAL CREDIT UNION
Berkeley, CA
Sep 1989 to Jun 1991
Operation Manager CAL BERKELEY FEDERAL CREDIT UNION
San Francisco, CA
Jun 1990 to Sep 1990
Assistant Financial Advisor
Apr 2012 to Present
Senior Manager/Financial Planning & Analysis OASIS CAPITAL VENTURES, LLC
Danville, CA
Sep 2007 to Sep 2011
Senior Manager ADVANCED EQUITIES, INC
San Francisco, CA
Nov 2005 to Jun 2007
Vice President SAN FRANCISCO CENTER
San Francisco, CA
Oct 2001 to Sep 2005
Relationship Manager/Senior Financial Adviser STOCKWALK.COM/M.ONE INVESTMENT SECURITIES
San Francisco, CA
Aug 1995 to Oct 2001
Financial Consultant/Operation Manager/Trader INTERNATIONAL CHI MEI TRADING
South San Francisco, CA
Dec 1994 to Jul 1995
Account Executive/Marketing Specialist MONEY TREE GEM COMPANY
San Francisco, CA
Jun 1991 to Dec 1994
Sales Manager CAL BERKELEY FEDERAL CREDIT UNION
Berkeley, CA
Sep 1989 to Jun 1991
Operation Manager CAL BERKELEY FEDERAL CREDIT UNION
San Francisco, CA
Jun 1990 to Sep 1990
Assistant Financial Advisor
Education:
University of California
Berkeley, CA
B.A. in Economic and Asian Studies
Berkeley, CA
B.A. in Economic and Asian Studies
Real Estate Brokers
James Hsu, Clarksville MD Real estate agent
view sourceSpecialties:
Buyer's Agent
Listing Agent
Listing Agent
Work:
Long and Foster Real Estate Inc.
12345 Wake Forest Road, Suite H, Clarksville, MD 21029
443 535-8000 (Office), 443 812-2860 (Cell), 443 535-0042 (Fax)
12345 Wake Forest Road, Suite H, Clarksville, MD 21029
443 535-8000 (Office), 443 812-2860 (Cell), 443 535-0042 (Fax)
Links:
Site
Medicine Doctors
James S. Hsu
view sourceSpecialties:
Pulmonary Critical Care Medicine, Sleep Medicine
Work:
Lung Center Of Nevada
9280 W Sunset Rd STE 312, Las Vegas, NV 89148
702 737-5864 (phone), 702 737-6885 (fax)
9280 W Sunset Rd STE 312, Las Vegas, NV 89148
702 737-5864 (phone), 702 737-6885 (fax)
Education:
Medical School
University of Utah School of Medicine
Graduated: 1991
University of Utah School of Medicine
Graduated: 1991
Procedures:
Allergy Testing
Pulmonary Function Tests
Vaccine Administration
Pulmonary Function Tests
Vaccine Administration
Conditions:
Bacterial Pneumonia
Obstructive Sleep Apnea
Abdominal Hernia
Abnormal Vaginal Bleeding
Acute Bronchitis
Obstructive Sleep Apnea
Abdominal Hernia
Abnormal Vaginal Bleeding
Acute Bronchitis
Languages:
English
Spanish
Spanish
Description:
Dr. Hsu graduated from the University of Utah School of Medicine in 1991. He works in Las Vegas, NV and specializes in Pulmonary Critical Care Medicine and Sleep Medicine. Dr. Hsu is affiliated with Southern Hills Hospital & Medical Center.
Name / Title
Company / Classification
Phones & Addresses
Owner
Capitol Cafe & Salad Bar
Eating Place
Eating Place
101 Constitution Ave NW, Washington, DC 20001
Owner
168 Restaurant
Eating Place
Eating Place
3288 Pierce St, Richmond, CA 94804
510 558-9168
510 558-9168
Vice President
Itouch Communications Inc
Other Telecommunications · Computer and Software Stores
Other Telecommunications · Computer and Software Stores
3 Twin Dolphin Dr STE 175, Redwood City, CA 94065
650 574-5561
650 574-5561
Managing
Focused Marketing LLC
Internet Marketing and E Commerce · Management Consulting Services
Internet Marketing and E Commerce · Management Consulting Services
2062 Kehoe Ave, San Mateo, CA 94403
Board of Directors
Varella LLC
Whol Jewelry/Precious Stones
Whol Jewelry/Precious Stones
871 Industrial Rd, San Carlos, CA 94070
650 591-8133
650 591-8133
HSU FAMILY LIMITED PARTNERSHIP
President
GRANDTREK, INC
6772 Rainbow Dr, San Jose, CA 95129
President
NIKKO RESTAURANT GROUP, INCORPORATED
2456 S El Camino Real, San Mateo, CA 94403
Youtube
James Hsu
view source
James Hsu
view source
James Hsu
view source
James Hsu
view source
James Hsu
view source
James Hsu
view source
James Hsu
view source
James Hsu
view sourceMyspace
Googleplus
James Hsu
Lived:
Taipei, taiwan
Riverside, CA
San Jose, CA
Cupertino, CA
Westwood, CA
Alhambra, CA
Van Nuys, CA
Riverside, CA
San Jose, CA
Cupertino, CA
Westwood, CA
Alhambra, CA
Van Nuys, CA
Work:
Helio
DirecTV
VantagePoint Venture Partners
Disney Consumer Products
DirecTV
VantagePoint Venture Partners
Disney Consumer Products
Education:
University of California, Los Angeles - Math Economics
James Hsu
Lived:
Long Beach, CA
Santa Barbara, CA
San Jose, CA
Santa Barbara, CA
San Jose, CA
Work:
OneStop Internet - Accountant (2011)
Education:
University of California, Santa Barbara - Business Economics
James Hsu
Work:
Sleepy Giant - Sr. Graphic Designer (2012)
OneScreen Inc. - Senior Graphic Designer (2009-2012)
OneScreen Inc. - Senior Graphic Designer (2009-2012)
Education:
California Polytechnic State University - Graphic Design
About:
Put a little about yourself so people know they've found the correct James. In the words of Christi Rochin, sometimes I wonder if I even am the correct James.
Tagline:
5'9" BAMF
James Hsu
Work:
Amazon.com - Software Development Engineer (2011)
Education:
Rutgers University - Computer Science
James Hsu
About:
James Hsu 認真工作的熟男。
James Hsu
Tagline:
WHO AM I?
James Hsu
Tagline:
No one likes change but babies in diapers.
James Hsu
Education:
Los Angeles, California
About:
Start over after a major setback
Classmates
James Hsu
view sourceSchools:
State University of New York at StonyBrook Stony Brook NY 1990-1994
Community:
Mikhail Fukshansky
James Hsu
view sourceSchools:
Mayberry Street Elementary School Los Angeles CA 1989-1994, Multnomah Elementary School Los Angeles CA 1994-1996, Belvedere Middle School Los Angeles CA 1996-1997, Thomas Starr King Middle School Los Angeles CA 1997-1999, Thomas Starr King Junior High School Los Angeles CA 1997-1999
Community:
Anthony Tony, Victor Ornelas
James Hsu
view sourceSchools:
St. Mary's Hall High School San Antonio TX 1997-1999
Community:
Elliot Malach, Kathleen Mccown, Rafael Loera, Anita Delana
James Hsu
view sourceSchools:
Academy Hall Houston TX 1986-1990
Community:
Kim Gonzales, Ginny Schempf, Jeff Cox
James Hsu
view sourceSchools:
Hobe Sound Christian Academy Hobe Sound FL 1996-2000
Community:
Linda Collins, Helane Rodencal
James Hsu
view sourceSchools:
Meyler Street Elementary School Torrance CA 1984-1988
Community:
Colleen Watson, Cameron Stone
James Hsu | Cedarlane Mid...
view source
James Hsu, Neenah High Sc...
view sourceFlickr
Plaxo
James Hsu
view source
James Hsu
view sourceOmega Front Webdesigns
jAMES hSU
view sourceDesigner at Prime Play
Get Report for James H Hsu from Bethesda, MD