Hyun Wook Shin

US Patent:

6344877, Feb 5, 2002

Filed:

Jun 12, 1997

Appl. No.:

08/873539

Inventors:

Sudhir Muniswamy Gowda - Ossining NY
Hyun Jong Shin - Ridgefield CT
Peter Hong Xiao - San Jose CA
Jungwook Yang - West Nyack NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04N 964

US Classification:

348245, 348308, 2502081

Abstract:

Disclosed is an image sensor including one or more dummy pixels that produce a reference signal which is used to compensate for errors within the devices of the main pixel cells. In one embodiment, at least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel. In another embodiment, an array of dummy pixels is used to correct for leakage current within the pixels during an electronic shutter mode of operation. The two techniques can be combined whereby both threshold voltage mismatch and leakage current are compensated for.

US Patent:

53595521, Oct 25, 1994

Filed:

Dec 6, 1993

Appl. No.:

8/163337

Inventors:

Sang H. Dhong - Mahopac NY
Hyun J. Shin - Mahopac NY
Wei Hwang - Armonk NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G05F 140

US Classification:

36518909

Abstract:

A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator. Along with further specific details of the voltage regulator, a preferred bandgap reference generator is described.

US Patent:

50031996, Mar 26, 1991

Filed:

Feb 26, 1990

Appl. No.:

7/484949

Inventors:

Hyun J. Shin - Mahopac NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H03K 1901
H03K 1708

US Classification:

307446

Abstract:

An ECL circuit having an output circuit with improved pull-down characteristics. An active pull-down circuit is provided by a p-channel JFET which includes a back gate connection or a merged p-channel JFET/NPN device. The gate and/or back gate are switched, providing a lowering of the device impedance during switching of the device from pull-up to pull-down operation, resulting in an improved pull-down speed.

US Patent:

54184770, May 23, 1995

Filed:

Apr 22, 1993

Appl. No.:

8/052005

Inventors:

Sang H. Dhong - Mahopac NY
Hyun J. Shin - Mahopac NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03R 19094

US Classification:

326 71

Abstract:

A pull-down circuit for a TTL compatible data output buffer uses NMOS devices. The pull-down circuit comprising two NMOS stages. Namely, a diode configuration stage where the gate and drain electrodes are shorted together during pull-down and a common-source stage. Both PMOS and NMOS devices are used for shorting the gate and drain electrodes.

US Patent:

58981683, Apr 27, 1999

Filed:

Jun 12, 1997

Appl. No.:

8/873610

Inventors:

Sudhir Muniswamy Gowda - Ossining NY
Hyun Jong Shin - Ridgefield CT
Peter Hong Xiao - San Jose CA
Jungwook Yang - West Nyack NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04N 314
H04N 5335

US Classification:

2502081

Abstract:

Disclosed is an image sensing device having a reduced number of transistors within each imager cell as compared to prior art devices. Each imager cell includes a photosensitive element providing a photocharge responsive to incoming light, and first, second and third transistors. The first transistor is coupled to an activation line, e. g. , a row select line, that carries an activation signal to a first plurality of imager cells to selectively activate cells for image data readout. This transistor transfers the photocharge towards a reference circuit node within the image cell in response to the activation signal. The second transistor is operably coupled to the first transistor, and is operative to selectively set a voltage level at the reference node. The third transistor has a control terminal coupled to the reference node, and an output terminal coupled to an output data bus common to a second plurality of image cells, e. g. , a column of cells.

US Patent:

50755668, Dec 24, 1991

Filed:

Dec 14, 1990

Appl. No.:

7/628252

Inventors:

Hyun J. Shin - Mahopac NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1762

US Classification:

307243

Abstract:

A high speed multiplexer circuit is described which includes a plurality of input bipolar transistors and a reference bipolar transistor. The input and reference transistors have their emitters commonly coupled to an emitter current supply and their collectors coupled to a collector supply. The collector of the reference transistor is coupled to the collector supply through an impedance. A reference potential is connected to the base of the reference bipolar transistor and biases it for conduction. An input signal to be multiplexed is connected to the base of each of the input bipolar transistors and a diode circuit is coupled between the base of each of the input bipolar transistors and a switch input. A switch input, in a first state, causes the diode circuit to conduct and clamp the base of an input transistor, to prevent it from responding to a signal input. The switch input also manifests a second state which renders the diode circuit non-conductive and enables an input transistor to conduct in response to an input signal.

US Patent:

54539536, Sep 26, 1995

Filed:

Jul 27, 1994

Appl. No.:

2/281236

Inventors:

Sang H. Dhong - Mahopac NY
Hyun J. Shin - Mahopac NY
Wei Hwang - Armonk NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G05F 324

US Classification:

36518909

Abstract:

A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator. Along with further specific details of the voltage regulator, a preferred bandgap reference generator is described.

US Patent:

58777156, Mar 2, 1999

Filed:

Jun 12, 1997

Appl. No.:

8/873537

Inventors:

Sudhir Muniswamy Gowda - Ossining NY
Hyun Jong Shin - Ridgefield CT
Peter Hong Xiao - San Jose CA
Jungwook Yang - West Nyack NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04N 140
H03M 146

US Classification:

341122

Abstract:

Disclosed is a circuit for performing correlated double sampling entirely in the digital domain. In an exemplary embodiment, the circuit includes a plurality of comparators, each having a first input coupled to an associated data line for receiving first and second signals in first and second sampling intervals, respectively. A time varying reference signal is applied to the second input of each comparator. A plurality of up/down counters are coupled to respective ones of the comparators, and each is operable to count in a first direction during the first sampling interval and in an opposite direction during the second sampling interval. Each up/down counter is caused to stop counting when the amplitude of the variable reference signal substantially equals the amplitude of the respective first or second signal. As a result, each up/down counter provides an output representing a subtraction of one of said first or second signals from the other. The invention has particular utility when used in conjunction with a CMOS image sensor.