Hyun Kil Shin

US Patent:

6344877, Feb 5, 2002

Filed:

Jun 12, 1997

Appl. No.:

08/873539

Inventors:

Sudhir Muniswamy Gowda - Ossining NY
Hyun Jong Shin - Ridgefield CT
Peter Hong Xiao - San Jose CA
Jungwook Yang - West Nyack NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04N 964

US Classification:

348245, 348308, 2502081

Abstract:

Disclosed is an image sensor including one or more dummy pixels that produce a reference signal which is used to compensate for errors within the devices of the main pixel cells. In one embodiment, at least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel. In another embodiment, an array of dummy pixels is used to correct for leakage current within the pixels during an electronic shutter mode of operation. The two techniques can be combined whereby both threshold voltage mismatch and leakage current are compensated for.

US Patent:

58981683, Apr 27, 1999

Filed:

Jun 12, 1997

Appl. No.:

8/873610

Inventors:

Sudhir Muniswamy Gowda - Ossining NY
Hyun Jong Shin - Ridgefield CT
Peter Hong Xiao - San Jose CA
Jungwook Yang - West Nyack NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04N 314
H04N 5335

US Classification:

2502081

Abstract:

Disclosed is an image sensing device having a reduced number of transistors within each imager cell as compared to prior art devices. Each imager cell includes a photosensitive element providing a photocharge responsive to incoming light, and first, second and third transistors. The first transistor is coupled to an activation line, e. g. , a row select line, that carries an activation signal to a first plurality of imager cells to selectively activate cells for image data readout. This transistor transfers the photocharge towards a reference circuit node within the image cell in response to the activation signal. The second transistor is operably coupled to the first transistor, and is operative to selectively set a voltage level at the reference node. The third transistor has a control terminal coupled to the reference node, and an output terminal coupled to an output data bus common to a second plurality of image cells, e. g. , a column of cells.

US Patent:

58777156, Mar 2, 1999

Filed:

Jun 12, 1997

Appl. No.:

8/873537

Inventors:

Sudhir Muniswamy Gowda - Ossining NY
Hyun Jong Shin - Ridgefield CT
Peter Hong Xiao - San Jose CA
Jungwook Yang - West Nyack NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04N 140
H03M 146

US Classification:

341122

Abstract:

Disclosed is a circuit for performing correlated double sampling entirely in the digital domain. In an exemplary embodiment, the circuit includes a plurality of comparators, each having a first input coupled to an associated data line for receiving first and second signals in first and second sampling intervals, respectively. A time varying reference signal is applied to the second input of each comparator. A plurality of up/down counters are coupled to respective ones of the comparators, and each is operable to count in a first direction during the first sampling interval and in an opposite direction during the second sampling interval. Each up/down counter is caused to stop counting when the amplitude of the variable reference signal substantially equals the amplitude of the respective first or second signal. As a result, each up/down counter provides an output representing a subtraction of one of said first or second signals from the other. The invention has particular utility when used in conjunction with a CMOS image sensor.

US Patent:

62752596, Aug 14, 2001

Filed:

Feb 2, 1998

Appl. No.:

9/017094

Inventors:

Sudhir Muniswamy Gowda - Ossining NY
Hyun Jong Shin - Ridgefield CT
Peter Hong Xiao - San Jose CA
Jungwook Yang - West Nyack NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04N 5235
G03B 700
H03M 162

US Classification:

348229

Abstract:

The present invention relates to an automatic gain control circuit in which the automatic gain control function is performed entirely in the digital domain. In an illustrative embodiment, the digital automatic gain control circuit for an image sensor having associated therewith an analog-to digital (A/D) converter for converting analog electrical signals from the image sensor to corresponding digital codes, includes a min/max detector for determining minimum and maximum electrical signal values from the digital codes of the A/D converter for each frame of image. A filter coupled to the min/max detector dampens instantaneous changes of the minimum and maximum values by filtering to provide filtered minimum and maximum values. A digital-to-analog (D/A) converter coupled to the filter generates minimum and maximum analog reference voltages corresponding to the respective minimum and maximum filtered values, the reference voltages being applied to the A/D converter to control associated amplitudes of the digital codes provided thereby.

US Patent:

59202742, Jul 6, 1999

Filed:

Aug 5, 1997

Appl. No.:

8/906595

Inventors:

Sudhir Muniswamy Gowda - Ossining NY
Hyun Jong Shin - Ridgefield CT
Peter Hong Xiao - San Jose CA
Jungwook Yang - West Nyack NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 112

US Classification:

341155

Abstract:

Disclosed is an image sensor having A/D conversion circuitry coupled to column data lines of an image sensor array. The A/D conversion circuitry digitizes analog signals on the column data lines, each representing intensity of light incident upon an active imager cell. Higher resolution is provided for darker light levels than for bright light levels, such that a high resolution image is obtained with less storage data than would otherwise be required. In one embodiment, the A/D conversion circuitry includes a plurality of comparators, each having a first input coupled to one or more column data lines and a second input coupled to receive a time-varying reference signal, and a plurality of n-bit counters coupled to the comparator outputs. An n-bit to m-bit converter nonlinearly maps n-bit codes to m-bit codes and provides the m-bit codes to an m-bit D/A converter which produces the time-varying reference signal. In another embodiment, the A/D conversion circuitry is comprised of a non-uniform successive approximation A/D converter.

US Patent:

51626683, Nov 10, 1992

Filed:

May 4, 1992

Appl. No.:

7/880286

Inventors:

Chih-Liang Chen - Briarcliff NY
Sang H. Dhong - Mahopac NY
Hyun J. Shin - Mahopac NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 301

US Classification:

3072968

Abstract:

Novel boosted power supplies are disclosed for an internal, on-chip regulator circuit which includes a differential amplifier coupler to a series regulating element operating as a source follower, and in which a voltage pump circuit is provided to generate a boosted power supply for the differential amplifier. The voltage pump preferably includes a ring oscillator for supplying pulses for the voltage pump. The new on-chip voltage regulators are designed for n-well CMOS technology circuits, and can be applied to BiCMOS as well as n-well CMOS circuits. The new circuits utilize voltage boosting techniques to increase the potential at the gate of the series regulating element operating as a source follower, and also improve the power supply rejection. Furthermore, these circuits preferably use clamping diodes to limit negative voltage swings at the gate of the series regulating element and to improve the settling time of the voltage regulator circuit. The on-chip regulator circuits are well suited for small dropout voltage regulator applications, have less external power supply sensitivity, use a clamping diode to improve the settling time of the feedback loop, and can utilize either static or dynamically controlled pump circuitry.

US Patent:

61150665, Sep 5, 2000

Filed:

Jun 12, 1997

Appl. No.:

8/876694

Inventors:

Sudhir Muniswamy Gowda - Ossining NY
Hyun Jong Shin - Ridgefield CT
Peter Hong Xiao - San Jose CA
Jungwook Yang - Nyack NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04N 5335

US Classification:

348308

Abstract:

A CMOS image sensor is provided in which correlated double sampling is performed entirely in the digital domain. In an exemplary embodiment, the image sensor includes a plurality of imager cells arranged in rows and columns, where the imager cells of a particular column are coupled to a column data line of that column. Each active imager cell is capable of selectively providing a first output on an associated column data line indicative of a reset level during a first sampling interval. During a second sampling interval, each active imager cell provides a signal output on the associated column data line indicative of an amount of light incident upon that imager cell. At least one analog to digital (A/D) converter is coupled to the column data lines and converts the first and signal outputs on each column data line to first and second digital codes, respectively, to complete a correlated double sampling operation. The invention eliminates the need for analog capacitors to store the reset and signal levels.