Gregory A Arlow

US Patent:

6600375, Jul 29, 2003

Filed:

Sep 12, 2001

Appl. No.:

09/952730

Inventors:

Alfred W. Morse - Ellicott City MD
Gregory A. Arlow - Southampton NJ

Assignee:

Northrop Grumman Corporation - Los Angeles CA

International Classification:

H03F 304

US Classification:

330296, 330 51, 330285

Abstract:

A source modulator circuit for an amplifier including a silicon carbide (SiC) static induction transistor (SIT) having a grounded gate, a source and a drain, includes: a source bias voltage supply connected to the source of the transistor; a drain voltage supply connected between the source and drain of the transistor; and a shunt circuit for directing current from the drain voltage supply around the source voltage supply to said source; whereby power dissipation by the source voltage supply is minimized. The shunt circuit includes a field effect transistor (FET) switch responsive to a control signal from a gated feedback operational amplifier for turning on the quiescent current of the SIT and setting the voltage applied to the source to a desired source voltage level.

US Patent:

6943640, Sep 13, 2005

Filed:

Jun 5, 2003

Appl. No.:

10/455544

Inventors:

Gregory Alan Arlow - Southampton NJ, US

Assignee:

Lockhead Martin Corporation - Bethesda MD

International Classification:

H03K007/00

US Classification:

332106, 332107, 342202, 342203, 323270, 323271, 34087018, 34087019

Abstract:

A current source modulator () provides power to radar transmitters. The modulator comprises a power supply () providing, when enabled, a known current to a storage capacitor (). A comparator circuit () provides a signal (V) when voltage (V) across the storage capacitor () falls a reference voltage, and an enable circuit () responds to the comparator signal (V) and an ON command signal to enable the power supply (). The modulator () further includes a network (N) associated with the comparator circuit () to retain the value of the signal (provide hysteresis) when the voltage across the storage capacitor is above the reference voltage. The modulator () may include a second network (N) associated with a second comparator circuit, operable to retain a second signal when capacitor () voltage Vis above a reference voltage. In this aspect, there is a rapid charge and a trickle charge that reduces any charging overshoot.

US Patent:

7034556, Apr 25, 2006

Filed:

Nov 5, 2003

Appl. No.:

10/702001

Inventors:

Gregory A. Arlow - Southampton NJ, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G01R 31/02
H05B 1/00

US Classification:

324760, 702130, 713322

Abstract:

A power solid-state device is pulsed from a controlled pulse source, which generates heat in the chip. Similar or identical pulses are applied to a software or equivalent electrical hardware temperature simulator, for predicting the chip temperature. The output of the simulator is monitored, and the controlled pulse source is inhibited in the event that the predicted chip temperature exceeds a limit. A delay may be introduced between the pulse generation and application to the chip. Additional temperatures associated with the chip heat sink may be combined with the chip temperature.

US Patent:

7332920, Feb 19, 2008

Filed:

Sep 14, 2005

Appl. No.:

11/226876

Inventors:

Gregory A. Arlow - Southampton NJ, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G01R 31/02
H05B 1/00

US Classification:

324760, 702130, 713322

Abstract:

A power solid-state device is pulsed from a controlled pulse source, which generates heat in the chip. Similar or identical pulses are applied to a software or equivalent electrical hardware temperature simulator, for predicting the chip temperature. The output of the simulator is monitored, and the controlled pulse source is inhibited in the event that the predicted chip temperature exceeds a limit. A delay may be introduced between the pulse generation and application to the chip. Additional temperatures associated with the chip heat sink may be combined with the chip temperature.

US Patent:

58014420, Sep 1, 1998

Filed:

Jul 22, 1996

Appl. No.:

8/681207

Inventors:

Robin E. Hamilton - Millersville MD
Paul G. Kennedy - Grasonville MD
John Ostop - Severna Park MD
Martin L. Baker - Sykesville MD
Gregory A. Arlow - Eldersburg MD
John C. Golombeck - Gambrills MD
Thomas J Fagan - Pittsburgh PA

Assignee:

Northrop Grumman Corporation - Los Angeles CA

International Classification:

H01L 2334

US Classification:

257714

Abstract:

Cooling of densely packaged semiconductor devices is achieved by microchannels which extract heat by forced convection and the use of fluid coolant located as close as possible to the heat source. The microchannels maximize heat sink surface area and provides improved heat transfer coefficients, thereby allowing a higher power density of semiconductor devices without increasing junction temperature or decreasing reliability. In its preferred embodiment, a plurality of microchannels are formed directly in the substrate portion of a silicon or silicon carbide chip or die mounted on a ground plane element of a circuit board and where a liquid coolant is fed to and from the microchannels through the ground plane. The microchannels comprise a plurality of closed-ended slots or grooves of generally rectangular cross section. Fabrication methods include deposition and etching, lift-off processing, micromachining and laser cutting techniques.

US Patent:

59982403, Dec 7, 1999

Filed:

May 4, 1998

Appl. No.:

9/071776

Inventors:

Robin E. Hamilton - Millersville MD
Paul G. Kennedy - Grasonville MD
John Ostop - Severna Park MD
Martin L. Baker - Sykesville MD
Gregory A. Arlow - Eldersburg MD
John C. Golombeck - Gambrills MD
Thomas J. Fagan - Pittsburgh PA

Assignee:

Northrop Grumman Corporation - Los Angeles CA

International Classification:

H01L 2144

US Classification:

438122

Abstract:

Cooling of densely packaged semiconductor devices is achieved by microchannels which extract heat by forced convection and the use of fluid coolant located as close as possible to the heat source. The microchannels maximize heat sink surface area and provides improved heat transfer coefficients, thereby allowing a higher power density of semiconductor devices without increasing junction temperature or decreasing reliability. In its preferred embodiment, a plurality of microchannels are formed directly in the substrate portion of a silicon or silicon carbide chip or die mounted on a ground plane element of a circuit board and where a liquid coolant is fed to and from the microchannels through the ground plane. The microchannels comprise a plurality of closed-ended slots or grooves of generally rectangular cross section. Fabrication methods include deposition and etching, lift-off processing, micromachining and laser cutting techniques.