Fen S Chen

US Patent:

20090006014, Jan 1, 2009

Filed:

Jun 27, 2007

Appl. No.:

11/769265

Inventors:

Kaushik Chanda - Fishkill NY, US
Fen Chen - Williston VT, US
Paul S. McLaughlin - Poughkeepsie NY, US
Ernest Y. Wu - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R 27/26
G01B 21/28

US Classification:

702 65, 702156

Abstract:

A method for determining a line-to-line spacing of a device. The method includes experimentally determining a slope k, experimentally determining a slope kand determining a line-to-line spacing of a device from the slope kand the slope k. A structure for performing the method includes a non-destructive line-to-line spacing characterization macro.

US Patent:

20130161791, Jun 27, 2013

Filed:

Feb 21, 2013

Appl. No.:

13/772493

Inventors:

International Business Machines Corporation - Armonk NY, US
Fen Chen - Williston VT, US
Baozhen Li - South Burlington VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 49/02

US Classification:

257532

Abstract:

The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.