Xiang Dong Zou

US Patent:

7487502, Feb 3, 2009

Filed:

Feb 19, 2003

Appl. No.:

10/370251

Inventors:

Hong Wang - Fremont CA, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
John Shen - San Jose CA, US
Xinmin Tian - Union City CA, US
Milind Girkar - Sunnyvale CA, US
Perry Wang - San Jose CA, US
Piyush Desai - Pleasanton CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/46
G06F 9/44
G06F 9/45

US Classification:

718102, 717127, 703 22

Abstract:

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

US Patent:

7743233, Jun 22, 2010

Filed:

Apr 5, 2005

Appl. No.:

11/100032

Inventors:

Hong Wang - Fremont CA, US
Gautham N. Chinya - Hillsboro OR, US
Richard A. Hankins - San Jose CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
John Shen - San Jose CA, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Jason W. Brandt - Austin TX, US
Prashant Sethi - Folsom CA, US
Douglas M. Carmean - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Scott Dion Rodgers - Hillsboro OR, US
Ryan N. Rakvic - Palo Alto CA, US
John L. Reid - Portland OR, US
David K. Poulsen - Champaign IL, US
Sanjiv M. Shah - Champaign IL, US
James Paul Held - Portland OR, US
James Charles Abel - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/00

US Classification:

712220

Abstract:

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

US Patent:

7882339, Feb 1, 2011

Filed:

Jun 23, 2005

Appl. No.:

11/165639

Inventors:

Quinn A. Jacobson - Sunnyvale CA, US
Hong Wang - Fremont CA, US
John Shen - San Jose CA, US
Gautham N. Chinya - Hillsboro OR, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivnandan D. Kaushik - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

US Classification:

712244

Abstract:

A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

US Patent:

8010969, Aug 30, 2011

Filed:

Jun 13, 2005

Appl. No.:

11/151809

Inventors:

Richard A. Hankins - San Jose CA, US
Gautham N. Chinya - Hillsboro OR, US
Hong Wang - Fremont CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant E. Bigbee - Scottsdale AZ, US
John P. Shen - San Jose CA, US
Trung A. Diep - San Jose CA, US
Xiang Zou - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Paul M. Petersen - Champaign IL, US
Sanjiv M. Shah - Champaign IL, US
Ryan N. Rakvic - Palo Alto CA, US
Prashant Sethi - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00
G06F 9/46
G06F 7/38

US Classification:

719318, 718100, 712235

Abstract:

A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

US Patent:

8332619, Dec 11, 2012

Filed:

Dec 8, 2011

Appl. No.:

13/314826

Inventors:

Quinn A. Jacobson - Sunnyvale CA, US
Hong Wang - Fremont CA, US
John P. Shen - San Jose CA, US
Gautham N. Chinya - Hillsboro OR, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivnandan D. Kaushik - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

US Classification:

712220

Abstract:

A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

US Patent:

20050166039, Jul 28, 2005

Filed:

Nov 5, 2004

Appl. No.:

10/982261

Inventors:

Hong Wang - Fremont CA, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
John Shen - San Jose CA, US
Xinmin Tian - Union City CA, US
Milind Girkar - Sunnyvale CA, US
Perry Wang - San Jose CA, US
Piyush Desai - Pleasanton CA, US

International Classification:

G06F009/30

US Classification:

712227000, 712244000

Abstract:

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

US Patent:

20070006231, Jan 4, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/173326

Inventors:

Hong Wang - Fremont CA, US
John Shen - San Jose CA, US
Ed Grochowski - San Jose CA, US
James Held - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivnandan Kaushik - Portland OR, US
Gautham Chinya - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Per Hammarlund - Hillsboro OR, US
Xinmin Tian - Union City CA, US
Anil Aggarwal - Portland OR, US
Scott Rodgers - Hillsboro OR, US
Prashant Sethi - Folsom CA, US
Baiju Patel - Portland OR, US
Richard Hankins - San Jose CA, US

International Classification:

G06F 9/46

US Classification:

718100000

Abstract:

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

US Patent:

20110087867, Apr 14, 2011

Filed:

Dec 16, 2010

Appl. No.:

12/970040

Inventors:

Quinn A. Jacobson - Sunnyvale CA, US
Hong Wang - Fremont CA, US
John Shen - San Jose CA, US
Gautham N. Chinya - Hillsboro OR, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivnandan D. Kaushik - Portland OR, US

International Classification:

G06F 9/44

US Classification:

712244, 712E0906

Abstract:

A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.